Memory device for repairing a neighborhood of rows in a...

Details Memory device for repairing a neighborhood of rows in a... Memory device for repairing a neighborhood of rows in a...

2011-06-07

2011-06-07

Baderman, Scott T (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S006100, C714S006110, C714S006320, C365S200000, C711S153000

Reexamination Certificate

active

07958390

ABSTRACT:
A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N−1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N−1, N, and N+1 to a table stored in the memory device.

REFERENCES:
patent: 4523313 (1985-06-01), Nibby et al.
patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 4694454 (1987-09-01), Matsuura
patent: 5130777 (1992-07-01), Galbraith et al.
patent: 5278839 (1994-01-01), Matsumoto et al.
patent: 5313425 (1994-05-01), Lee et al.
patent: 5329488 (1994-07-01), Hashimoto
patent: 5359569 (1994-10-01), Fujita et al.
patent: 5379259 (1995-01-01), Fujita
patent: 5432729 (1995-07-01), Carson et al.
patent: 5469450 (1995-11-01), Cho et al.
patent: 5498979 (1996-03-01), Parlour et al.
patent: 5535173 (1996-07-01), Carre et al.
patent: 5579265 (1996-11-01), Devin
patent: 5642318 (1997-06-01), Knaack et al.
patent: 5701267 (1997-12-01), Masuda et al.
patent: 5708667 (1998-01-01), Hayashi
patent: 5742934 (1998-04-01), Shinohara
patent: 5748545 (1998-05-01), Lee et al.
patent: 5751647 (1998-05-01), O'Toole
patent: 5757700 (1998-05-01), Kobayashi
patent: 5784391 (1998-07-01), Konigsburg
patent: 5796694 (1998-08-01), Shirane
patent: 5815448 (1998-09-01), Horiguchi et al.
patent: 5831989 (1998-11-01), Fujisaki
patent: 5835396 (1998-11-01), Zhang
patent: 5835509 (1998-11-01), Sako et al.
patent: 5872790 (1999-02-01), Dixon
patent: 5909049 (1999-06-01), McCollum
patent: 5920502 (1999-07-01), Noda et al.
patent: 5943254 (1999-08-01), Bakeman, Jr. et al.
patent: 5986950 (1999-11-01), Joseph
patent: 6016269 (2000-01-01), Peterson et al.
patent: 6026476 (2000-02-01), Rosen
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6205564 (2001-03-01), Kim et al.
patent: 6216247 (2001-04-01), Creta et al.
patent: 6236587 (2001-05-01), Gudesen et al.
patent: 6407953 (2002-06-01), Cleeves et al.
patent: 6420215 (2002-07-01), Knall et al.
patent: 6438044 (2002-08-01), Fukuda
patent: 6446242 (2002-09-01), Lien et al.
patent: 6462988 (2002-10-01), Harari
patent: 6487749 (2002-12-01), Tsui
patent: 6498749 (2002-12-01), Cuppens et al.
patent: 6515923 (2003-02-01), Cleeves
patent: 6525953 (2003-02-01), Johnson
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6567287 (2003-05-01), Scheuerlein
patent: 6574145 (2003-06-01), Kleveland et al.
patent: 6591394 (2003-07-01), Lee et al.
patent: 6597595 (2003-07-01), Ichiriu et al.
patent: 6625073 (2003-09-01), Beffa
patent: 6658438 (2003-12-01), Moore et al.
patent: 6661730 (2003-12-01), Scheuerlein et al.
patent: 6728126 (2004-04-01), Issaq et al.
patent: 6728149 (2004-04-01), Akamatsu
patent: 6792565 (2004-09-01), Koyama
patent: 6868002 (2005-03-01), Saito et al.
patent: 6895490 (2005-05-01), Moore et al.
patent: 6996660 (2006-02-01), Moore et al.
patent: 7003619 (2006-02-01), Moore et al.
patent: 7062602 (2006-06-01), Moore et al.
patent: 7142471 (2006-11-01), Fasoli et al.
patent: 7178072 (2007-02-01), Mullins et al.
patent: 7212454 (2007-05-01), Kleveland et al.
patent: 7257733 (2007-08-01), Nadeau-Dostie et al.
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2002/0085431 (2002-07-01), Jeon et al.
patent: 2002/0124130 (2002-09-01), Iida et al.
patent: 2002/0162062 (2002-10-01), Hughes et al.
patent: 2002/0196687 (2002-12-01), Sauvageau et al.
patent: 2003/0021176 (2003-01-01), Hogan
patent: 2003/0115514 (2003-06-01), Ilkbahar et al.
patent: 2003/0115518 (2003-06-01), Kleveland et al.
patent: 2003/0120858 (2003-06-01), March et al.
patent: 2004/0008554 (2004-01-01), Kanamori et al.
patent: 2004/0100831 (2004-05-01), Knall et al.
patent: 2004/0153744 (2004-08-01), Driscoll
patent: 2004/0255089 (2004-12-01), Unno
patent: 2004/0257891 (2004-12-01), Kim et al.
patent: 2005/0044459 (2005-02-01), Scheuerlein et al.
patent: 2005/0078537 (2005-04-01), So et al.
patent: 2005/0081093 (2005-04-01), Joly et al.
patent: 2005/0094449 (2005-05-01), Hidaka
patent: 2005/0207244 (2005-09-01), Takenaka
patent: 2006/0139988 (2006-06-01), Tran et al.
patent: 2006/0140026 (2006-06-01), Ilkbahar et al.
patent: 2006/0291303 (2006-12-01), Kleveland et al.
patent: 2007/0136640 (2007-06-01), Jarrar
patent: 2007/0171753 (2007-07-01), Morgan et al.
patent: 2007/0174718 (2007-07-01), Fouquet-Lapar
patent: 2007/0266202 (2007-11-01), Mukaida
patent: 2008/0285365 (2008-11-01), Bosch et al.
patent: 2 265 031 (1993-09-01), None
patent: WO 99/14763 (1998-08-01), None
“A 16Mb Mask ROM with Programmable Redundancy,” Nsruka et al., ISSCC 1989/Session 10: Nonvolatile Memories/Paper THAM 10.1, 2 pages, Feb. 16, 1989.
“Circuit Technologies for 16 Mb DRAMs,” Mano et al., ISSCC 1987/Session 1: MEGABIT DRAMs/Paper WAM 1.6, 2 pages, Feb. 27, 1987.
“Method for Re-Directing Data Traffic in a Write-Once Memory Device,” U.S. Appl. No. 09/877,691, filed Jun. 8, 2001; inventors: James J. Tringali, Christopher S. Moore, Roger W. March, James E. Schneider, Derek Bosch, and Daniel C. Steere.
“Reed-Solomon Codes: An introduction to Reed-Solomon Codes: principles, architecture and implementation,” http://www.4i2i.com/reed—solomon—codes.htm, 8 pages.
“TP 9.2: A 30ns 64Mb DRAM with Build-in-Self-Test and Repair Function,” ISSCC 92 Session 9/Non-Volatile and Dynamic Rams/Paper 9.2, 2 pages, 1992.
“64M×8 Bit, 32M×16 Bit NAND Flash Memory,” Samsung Electronics, 39 pages.
“Exotic memories, diverse approaches,” 8 pages, www.ednasia.com, Sep. 2001.
“A Vertical Leap for Microchips: Engineers have discovered a way to pack more computing power into microcircuits: build them vertically as well as horizontally,” Thomas H. Lee, 8 pages.
“Three-Dimensional Memory Array and Method of Fabrication,” U.S. Appl. No. 09/560,626, filed Apr. 28, 2000; inventors: Johan Knall.
Zhang et al., “On-state reliability of amorphous silicon antifuses,” IEDM Digest of Technical Papers, pp. 551-554, 1995.
Shih et al., “Characterization and modeling of a highly reliable metal-to-metal antifuse for high-performance and high-density field-programmable gate arrays,” Proceedings of IEEE, Int. Reliability Physics Synp., 1997, pp. 25-33.
Office Action for U.S. Appl. No. 11/803,776, dated Sep. 17, 2009, 12 pages.
International Search Report and Written Opinion for PCT/US2008/006041, 10 pages, mailed Oct. 31, 2008.
Office Action for U.S. Appl. No. 11/803,776, 14 pages, Apr. 13, 2010.
Office Action for U.S. Appl. No. 11/803,776, 15 pages, Sep. 15, 2010.

Affiliated with

Also associated with

Rating

Memory device for repairing a neighborhood of rows in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device for repairing a neighborhood of rows in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device for repairing a neighborhood of rows in a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2722940