Memory device for reducing leakage current

Details Memory device for reducing leakage current Memory device for reducing leakage current

2007-03-20

2007-03-20

Auduong, Gene N (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S189050

Reexamination Certificate

active

11158492

ABSTRACT:
Disclosed is a memory device for reducing leakage current generated by a bridge between a word line and a bit line when the memory device is in a waiting mode. The memory device includes: N memory cell blocks each of which includes plurality of memory cell blocks, wherein N represents a natural number; (N+1) sense amp blocks corresponding to the N memory cell blocks; 2N switching blocks connecting the N memory cell blocks to the (N+1) sense amp blocks, respectively; and N controllers for controlling the 2N switching blocks, respectively, wherein the N controllers turn off the 2N switching blocks when the memory device is in a waiting mode, and the N controllers selectively turn on the 2N switching blocks when the memory device is in an operation mode.

REFERENCES:
patent: 6104645 (2000-08-01), Ong et al.
patent: 6128230 (2000-10-01), Amanai
patent: 6198685 (2001-03-01), Sudo et al.

Affiliated with

Also associated with

Rating

Memory device for reducing leakage current does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device for reducing leakage current, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device for reducing leakage current will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3744500