Memory device for rapid data access from memory cell

Details Memory device for rapid data access from memory cell Memory device for rapid data access from memory cell

2005-10-04

2005-10-04

Tran, M. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S230030

Reexamination Certificate

active

06952374

ABSTRACT:
A semiconductor memory device having sense amplifier array blocks between neighboring unit memory cell array blocks in a column direction, the semiconductor memory device includes a first sense amplifier driving line configured by passing the sense amplifiers in a row direction, a second sense amplifier driving line configured by passing the sense amplifiers in a row direction, a plurality of first NMOS transistors, which is disposed in the sense amplifier array block, for locally performing a pull-up operation of the first sense amplifier driving line in response to a first control signal, and a second NMOS transistor, which is disposed in a hole area, for performing a pull-down operation of the second sense amplifier driving line in response to a second control signal.

REFERENCES:
patent: 5325336 (1994-06-01), Tomishima et al.
patent: 6870205 (2005-03-01), Lee et al.
patent: 2001-101866 (2001-04-01), None

Affiliated with

Also associated with

Rating

Memory device for rapid data access from memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device for rapid data access from memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device for rapid data access from memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3454087