Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-07-14
2002-08-06
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S189011, C365S189020, C365S189050, C365S189120, C365S230010, C365S230080, C365S238500
Reexamination Certificate
active
06430651
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is related to a memory device for constituting a memory subsystem of a data processing apparatus. More specifically, the present invention is directed to such a memory device suitably used to a memory subsystem of such a type of data processing apparatus that a large amount of data is directly supplied from a storage apparatus having a large storage capacity.
Very recently, since operating speeds of microprocessors are increased, remarkable advances appear in highspeed operations/high performance of peripheral components capable of supporting microprocessors. For instance, as to memory devices, various future types of “synchronous DRAMs” have been proposed, e.g., “MoSys DRAM(MDRA)”, “Media DRAM”, and “SyncLink DRAM”, which are described in Japanese magazine “NIKKEI MICRODEVICE” entitled “Strong Competition on Post-SDRAM: Protocol Control Method is Acceptable?” issued in April, 1996, pages 74 to 83 (will be referred to a “publication No. 1” hereinafter). Thus, there is a trend such that these synchronous DRAMs are standardized as main memories of information processing appliances.
On the other hand, performance of microprocessors is drastically improved in connection with great progress of semiconductor technology and development in the RISC techniques. In particular, since semiconductor technology is considerably advanced, operating frequencies of semiconductor chips for constituting highspeed microprocessors may exceed 500 MHz. While such highspeed microprocessors are commercially available, performance of electronic systems with employment of this sort of highspeed processor is similarly improved.
However, the following problems are revealed when the above-explained: electronic systems are practically realized.
That is, in general, the above-described high performance microprocessors can have sufficiently high capabilities while processing data held in cache memories employed inside processors and in peripheral circuits thereof are accessible by these electronic components in high speeds. However, when huge problems such as scientific technical calculations are tried to be solved by these high performance microprocessors, data to be handled cannot be held in these cache memories. Therefore, there is a problem such that the actual performance of these microprocessors would be considerably lowered. In other words, since a so-called “cache miss” happens to occur, processor waiting states will occur while data are transferred from either main memory or memory subsystems of lower hierarchy to the cache memories. As a result, the processors are brought into idle states and the system performance would be greatly lowered. The degree in lowering of this system performance is described in, for example, “Pseudo Vector Processor based on Register Window and Superscalar Pipeine” written in Parallel Processing Symposium JSPP, published in 1992, pages 367 to 374 (will be referred to as a “publication No. 2” hereinafter).
In this publication No. 2, the pseudo vector processor is proposed so as to solve such a cache miss problem. Then, in this pseudo vector processor, while a large number of registers are provided within this vector processor, the memory access operations for either the main memory or the memory subsystem of the lower hierarchy are carried out in the pipeline manner, so that lowering of the performance caused by the data waiting time could be minimized.
However, in this pseudo vector processor, the throughput degree required for either the main memory or the memory subsystem of the lower hierarchy is extremely high, as compared with a throughput degree for a normal microprocessor system equipped with a general-purpose cache memory and required for either a main memory thereof or a memory subsystem of a lower hierarchy. This is because this approach by a pseudo vector processor is intended to hide an increase of latency in accessing to either the main memory or the memory subsystem of the lower hierarchy by employing the pipeline structure, not to reduce an data amount to be treated.
As a consequence, either the main memory or the memory subsystem of the lower hierarchy used for the above-explained pseudo vector processor is necessarily constituted by employing the multi-bank structure in order to realize a large memory capacity as well as a high throughput. In this multi-bank structure, a plurality of memory devices equipped with highspeed interfaces such as synchronous DRAMs are arranged in a parallel manner.
A higher need for either a main memory or a memory subsystem of a lower hierarchy with a large memory capacity and a high throughput is required other than the pseudo vector processor. Another approach to solve the each cache miss problem, different from the above-explained architecture, is described in Micro-vector processor Architectures” written in the research report by Information Processing Society of Japan published on Jun. 12, 1992, pages 17 to 24 (will be referred to as a “publication No. 3” hereinafter).
In the above-described publication, one approach has been proposed in order to avoid lowering of the effective memory access performance. That is, in such a case that the function of the vector processor is manufactured in a single semiconductor chip by utilizing the high integration technique, the multithread processing operation in the vector instruction level is carried out as to the problem in which a total number of memory access pipelines is restricted by the input/output pin neck. Also, in this case, the high throughput is required for either the main memory or the memory subsystem of the lower hierarchy. As a result, similar to the pseudo vector processor, it is required to prepare either the main memory or the memory subsystem of the lower hierarchy, which owns the multi-bank structure.
A common necessary subject matter for such systems with employment of the above-explained two different architectures is given as follows. That is, either a main memory having a high memory capacity/throughput or a memory subsystem having high memory capacity/throughput of a lower hierarchy must be realized by using a small amount of electronic components and made in low cost. In other words, this common necessary subject matter implies that such a memory system is required to be provided, and this memory system is matched with a trend in a low-cost/compact processor. If such a memory system could not be realized, then the system balance would be destroyed and therefore the system value would be lost.
Similarly, completely different systems have been proposed. That is, the “unified memory architecture (UMA)” system has been proposed as a measure capable of constructing relatively low-cost personal computers, in which a cache memory mounted outside a processor is reduced, and/or other memories (frame buffer and the like) than a main memory may function as this main memory. This new trend is disclosed in Japanese magazine “NIKKEI MICRODEVICE” entitled “US PC industries starting - - - reduction in total memory quantities” issued in February 1996, pages 42 to 62 (will be referred to as a “publication No. 4” hereinafter). This system described in the publication No. 4 is arranged by that there are two large flows in memory accesses.
As one memory access flow, there is such an access operation from the processor functioning as the main memory, whereas as another memory access, there is such a sequential access operation from the graphics controller as the frame buffer. Then, the above-explained memory access system is featured by employing such a mode that a plurality of access, streams may access one memory subsystem. It should be understood that the performance of the memory subsystem must be maintained to some extent so as to achieve the practically meaningful mode. To this end, some data supplying ideas are necessarily required in low cost (namely, suppressing of increase in total component quantity) without largely lowering the resultant throughput with respect to a plurality of access streams.
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Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Namazi Mehdi
Yoo Do Hyun
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