Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1996-05-14
2001-01-09
Gossage, Glenn (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S005000, C713S320000, C712S233000, C365S230030, C365S227000
Reexamination Certificate
active
06173379
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to the field of electronic storage devices. More specifically, the present invention relates to storing and transferring information onto electronic storage devices.
(2) Description of the Related Art
Electronic storage devices are well known in the art. Typically, such devices are used for storing information therein and retrieving information therefrom when desired. Data is written into or read from these devices, generally, under the control of a processor. The processor, typically, sends a control signal to a storage device indicating what operation will be performed in conjunction with that storage device, i.e., a read or a write operation. An address bus coupled between the processor and the storage device allows the processor to drive the storage device with an address signal pointing to a specific storage location in conjunction with which a read or a write operation is to be performed. Data is then transferred to/from the storage device via a data bus depending on whether a write or a read operation is being performed.
FIG. 1
is an example of a prior art processor
102
coupled to two memory devices
104
and
116
. The memory device
104
is coupled to the processor via a control line
108
, address bus
110
, and data bus
112
. A clock
114
sequences the operation of the processor, of the memory device
104
, and of a second memory device
116
. The second memory device
116
is coupled to the processor via address bus
110
, data bus
112
, and control line
108
. When it is desired to copy information from one memory onto the other memory, the processor accesses the respective memory location storing the information to be transferred, fetches that information and copies it onto the other memory device. The configuration shown in
FIG. 1
, however, is limited to the copying of only one quantum of data, such as a byte, word, or a quad word, in one clock cycle, as generally data bus
112
is physically limited to 16, 32, or 64 bits.
In some cases, it is desirable to copy the entire information stored in a storage device such as a memory, cache, register file, or the like, onto another storage device. For example, in a microprocessor executing instructions speculatively it is often desirable to have “architectural” information stored in a first storage device and “speculative” information stored into a second storage device. “Architectural information” is herein defined as information that the processor produces and stores when executing instructions without performing or using branch prediction. The architectural information is validated information and, hence, by definition, is always correct. “Speculative information” is herein defined as estimated information that the processor produces and stores when executing instructions in the path of a predicted branch. The speculative information is generally generated in response to a speculative prediction which is found to be either correct or incorrect during a validation stage which occurs later in a processor's pipeline. The speculative information is, thus, unvalidated and may be incorrect until validation. If the prediction, however, is found to be correct, the speculative information is identical to the architectural information. When the speculative information is found to be incorrect during the validation stage, it is necessary to copy, in a very short time, such as one clock cycle, the entire architectural information onto the device storing the speculative information. The implementation of such features requires two memory storage arrays that can operate independently and a means for expeditiously copying information from one array to the other array in preferably one clock cycle.
One solution to this problem would be routing data and control lines from each storage cell, of the first storage device, to a corresponding cell of the second storage device. Such configuration, however, is very difficult to implement and is essentially undesirable as it requires a relatively large silicon area. This configuration also negatively affects the performance of the storage devices by increasing the capacitance, resistance, and inductance of the lines, thereby decreasing the speed of the storage device.
What is needed then is a device capable of copying information from a first storage area onto a second storage area without incurring the overhead posed by routing relatively long conductors from each storage cell of the first storage area to a corresponding storage cell of the second storage area.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a memory device including an array of memory cells. Each cell includes a first memory sub-cell and a second memory sub-cell. The memory device also includes a device that copies information from the first sub-cell onto the second sub-cell.
REFERENCES:
patent: 5245575 (1993-09-01), Sasaki et al.
patent: 5287485 (1994-02-01), Umina et al.
patent: 5532958 (1996-07-01), Jiang et al.
patent: 5539691 (1996-07-01), Kozaru
patent: 5557225 (1996-09-01), Denham et al.
patent: 5603009 (1997-02-01), Konishi et al.
Chen Wayne W.
Chen Wenliang
Lo Roger Y.
Poplingher Mircea
Suryanarayanan Ganesh
Blakely , Sokoloff, Taylor & Zafman LLP
Gossage Glenn
Intel Corporation
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