Memory device employing address multiplexing

Details Memory device employing address multiplexing Memory device employing address multiplexing

1987-08-31

1989-02-21

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Signals

365189, G11C 1140, G11C 1300

Patent

active

048071927

ABSTRACT:
A memory device employing address multiplexing comprises a counter. An external address is initially set in the counter and a counter address value is incremented responsive to toggle of a column address strobe. The counted address value in the counter is supplied as an address signal directly to a column decoder or indirectly to the column decoder through an address buffer. The memory device may be provided with a switching logic circuit which switches the address bits in the counter depending on switching information so that it is possible to arbitrarily determine which address bits in the counter are to determine a nibble address.

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