Memory device delaying timing of outputting data in a test mode

Details Memory device delaying timing of outputting data in a test mode Memory device delaying timing of outputting data in a test mode

1993-05-28

1994-11-01

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Signals

365201, 365233, 3652335, G11C 1700

Patent

active

053612302

ABSTRACT:
The present invention relates to a memory device having reduced access time of memory cells in a test mode. The memory device forms, in the test mode, read data D.sub.R by applying Ex-OR processing to a plurality of data read from a memory cell array 11 by a data processing circuit 5, to provide the formed data to the outside through a data output circuit 6. The timing of the output of data to the outside is delayed, by delay circuit 12 in the test mode, than that in the normal operation by a time period corresponding to time required for the EX-OR processing in data processing circuit 5. Consequently, output of invalid data to the outside can be prevented, and thus access time of valid data can be reduced.

REFERENCES:
patent: 4630239 (1986-12-01), Reed et al.

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