Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2007-10-23
2007-10-23
Le, Thong Q. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S158000, C365S189011, C365S200000
Reexamination Certificate
active
11526753
ABSTRACT:
When normal bit lines BL3and /BL3are selected, spare bit lines SBL2and /SBL2are simultaneously selected, so that column select gates are placed in such a manner that these bit line pairs are connected to respective different read data bus pairs. The column select gates are distributed in placement so as not to cause a great difference in load capacitance between read data buses. A redundancy determination result is reflected on read data by activation of control signals φ1and φ2given immediately prior to a sense amplifier. Note that two sense amplifier may be provided with control signals φ1and φ2so as to select the outputs of one sense amplifier. With such a configuration adopted, it is possible to provide a memory device capable of performing high speed reading while realizing a redundancy replacement.
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Chinese Office Action, with English-language translation, dated Jan. 12, 2007.
Buchanan & Ingersoll & Rooney PC
Le Thong Q.
Renesas Technology Corp.
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