Memory device bit line sensing system and method that...

Details Memory device bit line sensing system and method that... Memory device bit line sensing system and method that...

2009-09-29

2010-12-21

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including signal clamping

C365S203000, C365S230060, C365S236000, C365S185210, C365S196000

Reexamination Certificate

active

07855922

ABSTRACT:
Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.

REFERENCES:
patent: 6031779 (2000-02-01), Takahashi et al.
patent: 6920079 (2005-07-01), Shibayama
patent: 7505310 (2009-03-01), Nagasawa et al.
patent: 2001/0035548 (2001-11-01), Wahlstrom
patent: 2006/0227090 (2006-10-01), Ishii
patent: 2007/0258313 (2007-11-01), Yu et al.

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