Memory device architecture having global memory array repair cap

Details Memory device architecture having global memory array repair cap Memory device architecture having global memory array repair cap

1999-09-27

2000-10-17

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Bad bit

36523004, 36523003, 36518902, 36523006, 36518509, 36518513, 36518511, G11C 710

Patent

active

061341606

ABSTRACT:
An architecture for a high-capacity high-speed semiconductor memory device is disclosed. The semiconductor memory device includes memory cell arrays (406) having local word lines and bit lines. The memory cell arrays (406) are further arranged into array groups (402a-402d and 404a-404d). The local word lines (410a-410d) of the memory cell arrays of the same group are commonly connected to global word lines (408). The array groups (402a-402d and 404a-404d) provide data access paths to their respective memory cells by sets of input/output (I/O) lines (416a-416d and 420a-420d). The I/O line sets (416a-416d and 420a-420d) are coupled to data amplifiers by interarray multiplexers (MUXs) (422a-422d). The interarray MUXs (422a-422d) enable defective global word lines of one array group to be replaced by redundant global word lines of an adjacent array group.

REFERENCES:
patent: 4253059 (1981-02-01), Bell et al.
patent: 4393475 (1983-07-01), Kitagawa et al.
patent: 4733394 (1988-03-01), Giebel

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