Memory device and system having a variable depth write...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring

Reexamination Certificate

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Details

C711S165000

Reexamination Certificate

active

07380092

ABSTRACT:
A variable depth write data buffer is provided in a memory device coupled to a master device by an interconnect structure in an embodiment of the present invention. The variable depth write data buffer reduces a delay, or W-R turnaround bubble, time between a read operation and a write operation of a memory device memory core. The variable depth write buffer is programmable to store 1 to 4 data packets in an embodiment of the present invention. The variable depth write data buffer may also be programmed for multiple memory device configurations. A method preloads write data without address information into a write data buffer and a subsequent WRITE command causes the previously loaded write data to be retrieved from the write data buffer and written to a memory core according to an embodiment of the present invention.

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