Static information storage and retrieval – Read/write circuit – Noise suppression
Reexamination Certificate
2006-05-23
2006-05-23
Le, Thong Q. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Noise suppression
C365S102000
Reexamination Certificate
active
07050345
ABSTRACT:
A memory device and method with reduced power consumption and improved noise performance. An illustrative embodiment provides a random access memory with an array of plural memory bit cells, having bit-latches coupled between bit-true pass-gates and bit-compliment pass-gates are organized as plural columns and rows. There are plural bit lines pairs aligned with the plural columns, each of the bit line pairs including a bit-true and a bit-compliment bit line. The bit cell pass-gates are electrically coupled to a bit-true and a bit-compliment line pair along each particular column. Plural word lines are aligned with the plural rows, each of the rows having an integer number, greater than one, of word lines aligned therewith. Each one of the integer numbers of word lines is electrically coupled to a fraction of the bit cells in its aligned row. The bit cell to word line coupling is arranged so that no two bit cells within each of the fractions of the plural bit cells are positioned adjacent to one another within the array.
REFERENCES:
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patent: 6002625 (1999-12-01), Ahn
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patent: 6579781 (2003-06-01), Hamilton et al.
Brown Daniel R.
Dan Brown Law Office
Le Thong Q.
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