Memory device and method using positive gate stress to...

Details Memory device and method using positive gate stress to... Memory device and method using positive gate stress to...

2005-11-22

2005-11-22

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290

Reexamination Certificate

active

06967873

ABSTRACT:
A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

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International Search Report for International Application No. PCT/US2004/030694, Feb. 9, 2005.
Written Opinion of the International Searching Authority for International Application No. PCT/US2004/030694, Feb. 9, 2005.

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