Memory device and method thereof

Details Memory device and method thereof Memory device and method thereof

2008-08-27

2010-12-28

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S230050, C365S189050

Reexamination Certificate

active

07859919

ABSTRACT:
The present application discloses a memory array where each memory bit cell of the array includes a level shifter. In addition, each memory bit cell includes a write port that includes pass gate that can include a p-type field effect transistor and an n-type field effect transistor. The control electrodes of the p-type field effect transistor and the n-type field effect transistor are connected together as part of a common node. In addition, a current electrode of the p-type field effect transistor and a current electrode of the n-type field effect transistor are connected together to form a common node.

REFERENCES:
patent: 4616342 (1986-10-01), Miyamoto
patent: 5546026 (1996-08-01), Lin et al.
patent: 5696721 (1997-12-01), McAdams et al.
patent: 5786723 (1998-07-01), Kim
patent: 5825205 (1998-10-01), Ohtsuka
patent: 5973955 (1999-10-01), Nogle et al.
patent: 6040991 (2000-03-01), Ellis-Monaghan et al.
patent: 6122191 (2000-09-01), Hirose et al.
patent: 6262598 (2001-07-01), Cairns et al.
patent: 6363011 (2002-03-01), Hirose et al.
patent: 6621758 (2003-09-01), Cheung et al.
patent: 6639827 (2003-10-01), Clark et al.
patent: 6654277 (2003-11-01), Hsu et al.
patent: 6728145 (2004-04-01), Knupfer et al.
patent: 6774696 (2004-08-01), Clark et al.
patent: 6834024 (2004-12-01), Frydel et al.
patent: 6842059 (2005-01-01), Wu
patent: 7088630 (2006-08-01), Hung et al.
patent: 7161827 (2007-01-01), Ramaraju et al.
patent: 7167392 (2007-01-01), Poplevine et al.
patent: 7239558 (2007-07-01), Poplevine et al.
patent: 7274603 (2007-09-01), Futatsuyama et al.
patent: 7292495 (2007-11-01), Kenkare et al.
patent: 2002/0080651 (2002-06-01), Tanzawa et al.
patent: 2003/0052371 (2003-03-01), Matsuzaki et al.
patent: 2005/0057976 (2005-03-01), Joo et al.
patent: 2005/0078508 (2005-04-01), Chan et al.
patent: 2006/0152255 (2006-07-01), Wang et al.
patent: 2006/0262620 (2006-11-01), Goldman et al.
patent: 2007/0002636 (2007-01-01), Campbell et al.
patent: 2007/0241804 (2007-10-01), Campardo et al.
patent: 2347567 (2000-06-01), None
patent: 08-051351 (1996-02-01), None
patent: 09-106677 (1997-04-01), None
U.S. Appl. No. 11/746,126, filed May 9, 2007.
U.S. Appl. No. 11/534,715, filed Sep. 25, 2006.
International Application No. PCT/US2009/048656, International Search Report and Written Opinion and Dec. 28, 2009.
International Search Report mailed Jul. 25, 2008 for PCT Application PCT/US08/61707, 2 pages.
Office Action mailed Jan. 29, 2008 for U.S. Appl. No. 11/534,715, filed on Sep. 25, 2006, 9 pages.
Office Action mailed May 28, 2008 for U.S. Appl. No. 11/534,715, filed on Sep. 25, 2006, 9 pages.
Final Office Action mailed Oct. 22, 2008 for U.S. Appl. No. 11/534,715, filed on Sep. 25, 2006, 8 pages.
Notice of Allowance mailed Mar. 3, 2009 for U.S. Appl. No. 11/534,715, filed on Sep. 25, 2006, 6 pages.
Notice of Allowance mailed Jul. 25, 2008 for U.S. Appl. No. 11/746,126, filed on May 9, 2007, 7 pages.
Search Report mailed Jun. 28, 2010 for EPC Application No. EP8754938.

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