Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1999-09-24
2000-07-11
Phan, Trong
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
365194, 365226, G11C 800, G11C 700
Patent
active
060882883
ABSTRACT:
A method of reducing power supply current transients in a memory array caused by a simultaneous change in logic state of numerous CMOS digital circuits during a memory write cycle. Write driver enable signals (ENT, ENC) and bitcell enable signals (WBC1-WBC24) are sequentially delayed in time during the write cycle through use of the propagation delay of inverters (INV1-INV24-7). The sequential time delay reduces the number of circuits that are simultaneously changing logic state at any given time during the write cycle. The power supply current transient is transformed from a single, large change in current to a series of smaller changes displaced in time from each other during the write cycle. The ground bounce of the power supply network attributed to the current transient is significantly reduced, such change in ground potential being directly related to the magnitude of the current transient and its rate of change with respect to time.
REFERENCES:
patent: 5287527 (1994-02-01), Delp et al.
patent: 5719818 (1998-02-01), Tovim et al.
patent: 5774411 (1998-06-01), Hsieh et al.
Sheffield Bryan D.
Spriggs Stephen W.
Brady III Wade James
Donaldson Richard L.
Moore J. Dennis
Phan Trong
Texas Instruments Incorporated
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