Memory device and method of operating the same

Details Memory device and method of operating the same Memory device and method of operating the same

2011-03-08

2011-03-08

Le, Vu A (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030

Reexamination Certificate

active

07903466

ABSTRACT:
A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array.

REFERENCES:
patent: 7551492 (2009-06-01), Kim
patent: 2005/0185468 (2005-08-01), Hosono et al.
patent: 2005/0265079 (2005-12-01), Shirota
patent: 1020060070734 (2006-06-01), None

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