Memory device and method of arranging signal and power lines

Details Memory device and method of arranging signal and power lines Memory device and method of arranging signal and power lines

2006-12-06

2009-12-08

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S207000, C365S208000, C365S226000, C365S230030

Reexamination Certificate

active

07630223

ABSTRACT:
A memory device and method for arranging signal and power lines includes a plurality of sub-memory cell arrays having a plurality of memory cells, a plurality of sense amplifiers to sense and amplify data from the plurality of memory cells, a plurality of power lines to provide power to the sense amplifiers, where at least one of the power lines is disposed over a first set of the sense amplifiers and the sub-memory cell arrays, and at least another one of the power lines is disposed over second set of the sense amplifiers and the sub-memory cell arrays.

REFERENCES:
patent: 5966340 (1999-10-01), Fujino et al.
patent: 6104630 (2000-08-01), Hidaka
patent: 6275407 (2001-08-01), Otsuka
patent: 6483763 (2002-11-01), Uchikoba et al.
patent: 2003-338185 (2003-11-01), None
English language abstract of Japanese Publication No. 2003-338185.

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