Memory device and method implementing wordline redundancy withou

Details Memory device and method implementing wordline redundancy withou Memory device and method implementing wordline redundancy withou

1988-04-01

1989-12-05

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, G11C 2900

Patent

active

048857203

ABSTRACT:
A redundant word decoder compares an incoming address signal with a list of defective addresses and, in response to the comparison, produces at least one comparison signal to control the propagation of a redundany driver signal along at least one redundant wordline. A main trigger receives the comparison signal and, in response thereto, controls a triggering of a main wordline driver to produce a main driver signal. The main wordline driver and the redundant word decoder are responsive to opposite states of the comparison signal, such that, for a given comparison signal, only one of the main driver signal and redundant driver signal is applied to a memory array.

REFERENCES:
patent: 3753244 (1973-08-01), Sumilas
patent: 4365319 (1982-12-01), Takemae
patent: 4441170 (1984-04-01), Folmsbee et al.
patent: 4928068 (1984-01-01), Baba
Fitzgerald et al., "Memory System with High Performance Word Redundancy", IBM Technical Disclosure Bulletin, vol. 19, No. 5, Oct. 1976, pp. 1638-1639.
Smith et al., "Laser Programmable Redundancy and Yield Improvement in a 64K DRAM", IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5 Oct. 1981.
Benevit et al., "A 256K Dynamic Random Access Memory", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982, pp. 857-861.
Fitzgerald et al., IBM Journal of Research Development, vol. 24, no. 3, May 1980, pp. 291-297, "Circuit Implemntation of Fusible Redindant Addresses . . . ".
Cenker et al., "A Fault Tolerant 64K DRAM", IEEE Transactions on Electrical Devices Col ED-26, No. 6, Jun. 1979, pp. 853-860.

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