Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-06-29
2003-04-15
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230060
Reexamination Certificate
active
06549479
ABSTRACT:
TECHNICAL FIELD
This invention relates to dynamic random access memory (“DRAM”) devices, and more particularly to refreshing the memory cells of a DRAM in a manner that minimizes the power consumed by the DRAM during a self-refresh mode of operation.
BACKGROUND OF THE INVENTION
Dynamic Random Access memories (“DRAMs”) are commonly used in a variety of electronic devices, such as computers. A high level block diagram of a typical DRAM is shown in FIG.
1
. The DRAM shown in
FIG. 1
is a synchronous dynamic random access memory (“SDRAM”)
10
, although the principles described herein are applicable to any memory device containing memory cells that must be refreshed. The SDRAM
10
includes an address register
12
that receives either a row address or a column address on an address bus
14
. The address bus
14
is generally coupled to a memory controller (not shown in FIG.
1
). Typically, a row address is initially received by the address register
12
and applied to a row address multiplexer
18
. The row address multiplexer
18
couples the row address to a number of components associated with either of two memory banks
20
,
22
depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks
20
,
22
is a respective row address latch
26
which stores the row address, and a row decoder
28
which applies various signals to its respective array
20
or
22
as a function of the stored row address. The row address multiplexer
18
also couples row addresses to the row address latches
26
for the purpose of refreshing the memory cells in the arrays
20
,
22
. The row addresses are generated for refresh purposes by a refresh controller
30
that normally includes a refresh counter (not shown in FIG.
1
).
After the row address has been applied to the address register
12
and stored in one of the row address latches
26
, a column address is applied to the address register
12
. The address register
12
couples the column address to a column address latch
40
. Depending on the operating mode of the SDRAM
10
, the column address is either coupled through a burst counter
42
to a column address buffer
44
, or to the burst counter
42
which applies a sequence of column addresses to the column address buffer
44
starting at the column address output by the address register
12
. In either case, the column address buffer
44
applies a column address to a column decoder
48
which applies various signals to respective sense amplifiers and associated column circuitry
50
,
52
for the respective arrays
20
,
22
.
Data to be read from one of the arrays
20
,
22
is coupled to the column circuitry
50
,
52
for one of the arrays
20
,
22
, respectively. The data is then coupled to a data output register
56
, which applies the data to a data bus
58
. Data to be written to one of the arrays
20
,
22
are coupled from the data bus
58
through a data input register
60
to the column circuitry
50
,
52
where it is transferred to one of the arrays
20
,
22
, respectively. A mask register
64
may be used to selectively alter the flow of data into and out of the column circuitry
50
,
52
, such as by selectively masking data to be written to the arrays
20
,
22
.
The above-described operation of the SDRAM
10
is controlled by a command decoder
68
responsive to high level command signals received on a control bus
70
. These high level command signals, which are typically generated by a memory controller (not shown in FIG.
1
), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the “*” designating the signal as active low. The command decoder
68
generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals. For example, driving the RAS* and CAS* inputs low with CKE* high will cause the SDRAM
10
to enter a self refresh mode. In the self refresh mode, the refresh controller
30
causes the memory cells in the arrays
20
,
22
to be periodically refreshed. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
Each of the memory arrays
20
,
22
contains a large number of memory cells arranged in rows and columns, each of which stores a bit of data. In a DRAM, the memory cells are implemented with respective capacitors. However, charge gradually leaks from a memory cell capacitor, thus making it necessary to periodically recharge the capacitor, which is a procedure known as a refresh of the memory cell. Memory cells are normally refreshed by periodically activating a row of memory cells, thereby coupling each memory cell in the activated row to a respective sense amplifier. The sense amplifier senses the voltage to which each memory cell was initially charged, and then charges or discharges each memory cell to the initial voltage.
A variety of techniques have been devised to refresh the memory cells of DRAMs. In some modes, the rows of memory cells that are to be refreshed are selected by applying corresponding row addresses to the DRAM. As mentioned above, in the self-refresh mode of operation, the addresses of rows that are to be refreshed are generated by circuitry internal to the DRAM in response to receipt of the self refresh command. In all cases, the refresh is controlled by the refresh controller
30
.
A block diagram of a portion of a typical prior art refresh controller
100
and a portion of a typical row address driver
102
are shown in FIG.
2
. The refresh controller
100
may be used in the refresh controller
30
in the SDRAM of
FIG. 1
, and the row address driver
102
may be used in the row decoder
28
in the SDRAM
10
of FIG.
1
. It will be understood that the refresh controller
100
and the row address driver
102
each include a large number of additional elements that have been omitted from
FIG. 2
in the interest of brevity. The refresh controller
100
includes an oscillator
104
that generates a periodic signal, as is well known in the art. The periodic signal from the oscillator
104
is applied to a clock input of a binary counter
108
. In the embodiment explained herein, the counter has 9 stages, and thus outputs
9
row address bits RA
0
-RA
8
arranged from the least significant bit RA
0
to the most significant bit RA
8
. However, it will be understood that a large or smaller number of address bits may be generated by the counter
108
depending upon the number of rows in the array. The output of the counter
108
is applied to one set of inputs to the multiplexer
18
(see, also, FIG.
1
). A second set of inputs to the multiplexer
18
is coupled to the address bus
14
(
FIG. 1
) through the address register
12
to receive a second set of row address bits RA
0
-RA
8
. In the self-refresh mode, an REF input to the multiplexer
18
from the command decoder
68
(
FIG. 1
) causes the multiplexer
18
to select the row address bits RA
0
-RA
8
from the counter
108
and apply them to the row address driver
102
(FIG.
1
).
The row address driver
102
includes a row pre-decoder
114
that receives the row address bits RA
0
-RA
8
from the multiplexer
18
and outputs pre-decoded row address signals, RA
0
<
0
:
1
>, RA
12
<
0
:
3
>, RA
34
<
0
:
3
>, and RA
56
<
0
:
3
>based on various combinations of the row addresses RA
0
-RA
8
. The row address signals RA
0
<
0
:
1
> consists of two signals RA<
0
> and RA<
1
> that correspond to the binary values of RA
0
. More specifically, when the address bit RA
0
is low, RA<
0
> is high and RA<
1
> is low. When the address bit RA
0
is high, RA<
0
> is low and RA<
1
> is high. The other pre-decoded row address signals are generated in a similar m
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Tan T.
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