Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2005-08-23
2005-08-23
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S189050, C365S233100
Reexamination Certificate
active
06934199
ABSTRACT:
A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.
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Johnson Brian
Johnson Christopher S.
Dorsey & Whitney LLP
Lebentritt Michael S.
Nguyen Hien
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