Memory device and method having data path with multiple...

Details Memory device and method having data path with multiple... Memory device and method having data path with multiple...

2006-04-18

2006-04-18

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Sipo/piso

C365S220000, C365S221000, C365S189030, C365S189080

Reexamination Certificate

active

07031215

ABSTRACT:
A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

REFERENCES:
patent: 5828664 (1998-10-01), Weir
patent: 5923899 (1999-07-01), Martin et al.
patent: 5995442 (1999-11-01), Toda et al.
patent: 5999458 (1999-12-01), Nishimura et al.
patent: 6032274 (2000-02-01), Manning
patent: 6084823 (2000-07-01), Suzuki et al.
patent: 6172938 (2001-01-01), Suzuki et al.
patent: 6185149 (2001-02-01), Fujioka et al.
patent: 6246614 (2001-06-01), Ooishi
patent: 6252804 (2001-06-01), Tomita
patent: 6317377 (2001-11-01), Kobayashi
patent: 6327205 (2001-12-01), Haq
patent: 6400617 (2002-06-01), Aikawa et al.
patent: 6515914 (2003-02-01), Keeth et al.
patent: 6606272 (2003-08-01), Oh et al.
patent: 6665223 (2003-12-01), Keeth et al.
patent: 6690609 (2004-02-01), Keeth et al.
patent: 6693836 (2004-02-01), Keeth et al.
patent: 6882579 (2005-04-01), Keeth et al.
patent: 6934900 (2005-08-01), Cheng et al.
patent: 2001/0000990 (2001-05-01), Matsudera et al.
patent: 2001/0019503 (2001-09-01), Ooishi
patent: 2002/0078468 (2002-06-01), Yazawa
patent: 2002/0133731 (2002-09-01), Johnson et al.
patent: 2002/0135501 (2002-09-01), Keeth et al.
patent: 2002/0178274 (2002-11-01), Kovacevic
patent: 2003/0043658 (2003-03-01), Keeth et al.
patent: 2003/0043659 (2003-03-01), Keeth et al.
patent: 2003/0043669 (2003-03-01), Keeth et al.
patent: 2003/0048668 (2003-03-01), Keeth et al.
patent: 2004/0085996 (2004-05-01), Sleeman
patent: 2004/0246783 (2004-12-01), Lee et al.
patent: 2004/0260964 (2004-12-01), Kuzmenka et al.

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