Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-02-07
2006-02-07
Peikari, B. James (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S100000, C711S103000, C711S004000, C711S154000, C365S185330, C365S185290, C365S185130, C365S185140, C365S189011, C365S234000, C365S236000, C365S185150
Reexamination Certificate
active
06996660
ABSTRACT:
The preferred embodiments described herein provide a memory device and method for storing and reading data in a write-once memory array. In one preferred embodiment, a plurality of bits representing data is inverted and stored in a write-once memory array. When the inverted plurality of bits is read from the memory array, the bits are inverted to provide the data in its original, non-inverted configuration. By storing data bits in an inverted form, the initial, un-programmed digital state of the memory array is redefined as the alternative, programmed digital state. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another. For example, the embodiments in which data bits are inverted can be used alone or in combination with the embodiments in which data is redirected.
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March Roger W.
Moore Christopher S.
Schneider James E.
Tringali J. James
Brinks Hofer Gilson & Lione
Li Zhuo H.
Matrix Semiconductor Inc.
Peikari B. James
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