Memory device and method for manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S315000, C257SE29300, C438S259000, C438S266000, C365S185010

Reexamination Certificate

active

07598563

ABSTRACT:
A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench.

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patent: WO 2004/057661 (2004-07-01), None
English Translation of a Chinese Office Action; Application No. 200510130178.9; Dated Jan. 18, 2008; State Intellectual Property Office of People's Republic of China; People's Republic of China.

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