Memory device and method for burn-in test

Details Memory device and method for burn-in test Memory device and method for burn-in test

2006-09-12

2006-09-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S230060, C365S230080

Reexamination Certificate

active

07106644

ABSTRACT:
A memory device and a method for burn in test are characterized by a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

REFERENCES:
patent: 5293340 (1994-03-01), Fujita
patent: 6005815 (1999-12-01), Nakano

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