Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reexamination Certificate
2001-11-15
2002-11-26
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S531000
Reexamination Certificate
active
06486885
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a memory device suitable for application as an image memory. Specifically, this invention relates to a semiconductor memory device making it possible to implement two-port operations for writing and reading while restraining an increase in the area of a chip.
FIG. 6
shows an example of a configuration of a conventional image memory
100
. The present image memory
100
has a DRAM (Dynamic Random Access Memory)
101
, SRAMs (Static Random Access Memory)
102
A and
102
B, each used as a buffer memory disposed on the data input side (serial-in side). The memory
100
also has a serial Y decoder
103
for selecting write addresses for the SRAMs
102
A and
102
B, based on a Y-direction component of a write address signal, SRAMs
104
A and
104
B each used as a buffer memory disposed on the data output side (serial-out side), and a serial Y decoder
105
for selecting read addresses for the SRAMs
104
A and
104
B, based on a Y-direction component of a read address signal.
Now, the SRAMs
102
A and
102
B on the data input side are disposed as halves of an array of the DRAM
101
and alternately perform a transfer operation so that the writing of data can be made sequentially. Similarly, the SRAMs
104
A and
104
B on the data output side are also disposed as halves of the array of the DRAM
101
and alternately carry out a transfer operation so that the reading of data can be sequentially made.
Further, the image memory
100
includes an X decoder
106
for selecting an X-direction address (transfer address) related to writing or reading with respect to the DRAM
101
, a write address counter
107
for generating a write address signal, a read address counter
108
for generating a read address signal, and an arbiter
109
used as an arbitration circuit for delaying write transfer when write and read transfer commands are brought into proximity with each other. In this case, the write transfer itself may be performed until the writing of data into the following SRAM (buffer memory) is completed, and there is sufficient lead-time to perform the write transfer.
For example, the image memory
100
shown in
FIG. 6
is used to perform a flicker-free signal process for preventing screen's flicker (dazzling) with the number of screens as two, for example.
FIG. 7
shows write and read address changes in the flicker-free signal process. In this case, respective video data (
1
W,
2
W, etc.) constituting one filed or frame are successively written into the image memory
100
. Further, respective video data (
1
R,
2
R, etc.) are continuously read twice in succession from the image memory
100
at a speed twice the speed of writing.
According to the image memory
100
shown in
FIG. 6
, since there are provided the buffer memories
102
A,
102
B,
104
A and
104
B therein, two-port operations for writing and reading can be performed without any problem even when the write and read transfer commands are brought into connection with each other. However, since the buffer memories
102
A,
102
b
,
104
a
and
104
B are large in size, it is inconvenient since the chip area of the image memory
100
will increase.
In recent years, there may be many cases in which a memory of a megabit class is constructed so as to be divided into a plurality of memory blocks (MAT division) which serve as separate memories respectively, from the restrictions in circuit length of word and bit lines. In this case, when read and write operations are performed with predetermined memory blocks, non-accessed memory blocks are placed in an inactivated state.,
OBJECTS OF THE INVENTION
The present invention has been made in view of the above circumstances, and an object of this invention is to provide a memory device capable of implementing two-port operations for writing and reading while not increasing the chip area.
Another object of this invention is to provide a memory device capable of implementing a synchronous two-port operation for writing and reading without use of a buffer memory.
Another object of this invention is to provide a semiconductor memory device capable of effectively utilizing non-accessed inactive areas.
SUMMARY OF THE INVENTION
In order to attain the above objects, according to an aspect of the present invention, a memory device for storing a sequential image data in succession and outputting the stored image data is provided. The memory device comprises a memory unit comprising N memory blocks, each memory blocks being capable of individual serving, a write address generator for generating a write address signal to write read into the memory unit and a read address generator for generating a read address signal to read from the memory unit. The memory unit further comprises a controller for controlling the write address signal and the read address signal so that each start address for writing and reading for each image data is shifted as unit of the memory block and the writing and reading operation are not simultaneously performed to same memory block, each image data having a size being equivalent to one of M blocks (M<N).
Also, each image data represents an image data for one field or one frame. Further, the image data for one field or one frame, which is written into the memory unit is continuously read out twice at a speed twice the speed at writing. The image data for one field or one frame, which is written into the memory unit is continuously read out twice at a speed twice the speed at writing to perform a flicker-free signal processing.
The memory device further comprises an arithmetic circuit for performing a certain signal process by obtaining access to the memory block in the memory unit, which is free from the write and read operation. The arithmetic circuit performs noise reduction processing and receives a current image data from a input terminal and a previous image data from the memory block that is free from the write and read operation. The arithmetic circuit performs the noise reduction processing to the current image data by using the previous image data to produce a noise reduced current image data.
The controller further replaces a predetermined number of bits from a most significant bit of the read address signal with a predetermined number of revised bits for selecting a memory block to read out the image data and replaces a predetermined number of bits from a most significant bit of the write address signal with a predetermined number of revised bits for selecting a memory block to write the image data.
REFERENCES:
patent: 4847809 (1989-07-01), Suzuki
patent: 5710604 (1998-01-01), Hodson et al.
patent: 5929832 (1999-07-01), Furukawa et al.
patent: 6067120 (2000-05-01), Horikawa et al.
patent: 6097404 (2000-08-01), Satoh et al.
patent: 2 582 423 (1986-11-01), None
Kondo Tetsujiro
Okumura Akihiro
Frommer William S.
Frommer & Lawrence & Haug LLP
Shallenburger Joe H.
Sony Corporation
Tung Kee M.
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