Memory device and memory system using same

Details Memory device and memory system using same Memory device and memory system using same

2003-01-24

2004-08-03

Le, Vu Anh (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06771531

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device including a non-volatile ferroelectric memory and a memory system using this memory device.
2. Description of the Related Art
Semiconductor memories, particularly FeRAMs using ferroelectric materials, are attracting attention as user-friendly devices providing both high speed access and non-volatile storage and offering the promise of increased capacity in the future.
An FeRAM is small in size and consumes low electric power and, at the same time, is resistant to shock. If progress is made in reducing the bit unit price along with the increase in capacity, it will also has promise as a future recording medium for sound or images.
Particularly, as promising means for improving the degree of integration, Japanese Patent Application No. 11-158632 and Japanese Unexamined Patent Publication (Kokai) No. 09-121032 propose a so-called “cross point type” ferroelectric memory.
FIG. 10
is a circuit diagram of an example of a cross point type ferroelectric memory.
This ferroelectric memory
10
has, as shown in
FIG. 10
, a memory cell array
11
, word driver (WRD DRV)
12
, plate (PLT DRV) driver
13
, and sense amplifier (S/A)
14
.
The memory cell array
11
is comprised of a plurality of (eight in
FIG. 10
) ferroelectric capacitors FC
101
to FC
108
forming individual memory cell arranged in a four-row, two-column matrix.
The memory cell array
11
is divided into two cell strings CST
11
and CST
12
.
The cell string CST
11
is configured by a pass transistor TR
101
comprised of an n-channel MOS transistor and ferroelectric capacitors FC
101
, FC
102
, fC
103
, and FC
104
arranged in the same column.
In the cell string CST
11
, first electrodes of the ferroelectric capacitors FC
101
, FC
102
, FC
103
, and FC
104
serving as four memory cells are commonly connected to one node electrode ND
11
connected to a bit line BL
11
via the pass transistor TR
101
.
The other electrodes of the ferroelectric capacitors FC
101
, FC
102
, FC
103
, and FC
104
are connected to different plate lines PL
11
, PL
12
, PL
13
, and PL
14
to thereby enable data to be written independently in the ferroelectric capacitors FC
101
, FC
102
, FC
103
, and FC
104
serving as the memory cells.
Note that data of the plurality of ferroelectric capacitors FC
101
, FC
102
, FC
103
, and FC
104
sharing the node electrode ND
11
is for example accessed all together continuously. Further, the accessed data is amplified by the sense amplifier
14
and rewritten.
The cell string CST
12
is configured by a pass transistor TR
102
comprised of an n-channel MOS transistor and ferroelectric capacitors FC
105
, FC
106
, FC
107
, and FC
108
arranged in the same column.
In the cell string CST
12
, first electrodes of the ferroelectric capacitors FC
105
, FC
106
, FC
107
, and FC
108
serving as four memory cells are commonly connected to one node electrode ND
12
connected to a bit line BL
12
via the pass transistor TR
102
.
The other electrodes of the ferroelectric capacitors FC
105
, FC
106
, FC
107
, and FC
108
are connected to different plate lines PL
11
, PL
12
, PL
13
, and PL
14
to thereby enable data to be independently written in the ferroelectric capacitors FC
105
, FC
106
, FC
107
, and FC
108
serving as the memory cells.
Note that the data of the plurality of ferroelectric capacitors FC
105
, FC
106
, FC
107
, and FC
108
sharing the node electrode ND
12
is for example accessed all together continuously. Further, the accessed data is amplified by the sense amplifier
14
and rewritten.
The gate electrodes of the pass transistors TR
101
and TR
102
of the cell strings CST
11
and CST
12
are connected to a common word line WL
11
.
A word driver
12
supplies for example a power supply voltage V
cc
+&agr; (&agr; is a voltage not less than the threshold voltage Vth of the pass transistor, for example 1V) to an addressed word line, i.e., WL
11
in the example of
FIG. 10
, and holds the pass transistors in a conductive state in units of cell units.
A plate driver
13
supplies the plate lines PL
11
to PL
14
addressed at the time of data access with a predetermined voltage 0V or V
cc
for writing or reading and rewriting data in the ferroelectric capacitor of the addressed memory cell and supplies unselected plate lines with a predetermined voltage V
cc
/2.
The sense amplifier
14
is connected to the bit lines BL
11
and BL
12
, latches, amplifies, and rewrites (refreshes) the data read to the bit lines BL
11
and BL
12
at the time of writing and reading.
The read operation in the ferroelectric memory
10
having such a configuration is carried out as follows.
For example, when driving the word line WL
11
by the word driver
12
, fixing the plate lines PL
12
to PL
14
to 0V by the plate driver
13
, and in that state driving the plate line PL
11
to V
cc
, the ferroelectric capacitors FC
101
and FC
105
discharge to the bit lines BL
11
and BL
12
.
The data can be read by sensing the potential difference produced by this by a differential type sense amplifier
14
.
Since the cross point type ferroelectric memory has one transistor shared by a plurality of capacitors, the number of elements per bit is effectively decreased. This is effective for reducing costs.
Summarizing the problem to be solved by the invention, as explained above, while a cross point type ferroelectric memory is advantageous from the viewpoint of degree of integration, it has the following limitations.
Namely, in the above cross point type semiconductor memory, since a plurality of capacitors are connected to a common node electrode of the memory string selected by the word line, when writing data into any one capacitor, voltage is also supplied to the unselected capacitors sharing the node electrode (this will be generally referred to as a “disturbance”).
The voltage supplied is not large enough to destroy the data by a single time, but if this is supplied a number of times without restraint, the data will gradually deteriorate and finally the data will be destroyed.
Accordingly, the number of disturbances has to be restricted by some measure or another.
In the above Japanese Unexamined Patent Publication (Kokai) No. 09-121032 etc., the memory is designed to be accessed in block units so as to establish an upper limit on the disturbances.
Namely, when any cell is accessed, the other cells in the same memory string which would be affected by a disturbance are also accessed and rewritten in a consecutive sequence.
Accordingly, when the number of cells connected to the common node electrode of a memory string is N, the upper limit of the number of disturbances is N−1 times.
In this case, however, when accessing a certain memory string, the other memory strings cannot be accessed until all of the cells connected to that string finish being read and rewritten.
Accordingly, the application of this to random access applications like that of for example a DRAM is basically impossible or results in very slow operation.
Further, general ferroelectric memories suffer from the problem of “film fatigue”. This is the deterioration of the polarization characteristic due to repeated inversion of polarization of the ferroelectric film. The number of rewrites is restricted by this.
In general, the number of rewrites of a ferroelectric film is considered to be to about 1E12 times. With use like a DRAM, therefore, the reliability cannot be guaranteed.
For the above reason, there was the problem that the cross point type ferroelectric memory was very limited in its usage.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory device able to make use of the non-volatility and high integration of a cross point type ferroelectric memory and yet able to improve the random accessibility of the same, reduce the number of rewrites, and facilitate control of the upper limit of disturbances and a memory system using the same.
To attain the above object, according to a first aspect of the present invention, there is pro

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