Memory device and memory system comprising a memory device...

Details Memory device and memory system comprising a memory device... Memory device and memory system comprising a memory device...

2008-10-09

2011-10-04

Nguyen, Dang (Department: 2824)

Static information storage and retrieval

Read/write circuit

Particular read circuit

C365S233100, C365S191000

Reexamination Certificate

active

08031539

ABSTRACT:
In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.

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Zheng Gu, Peter Gregorius, Daniel Kehrer, Lydia Neumann, Evelyn Neuscheler, Thomas Rickes, Hermann Ruckerbauer, Ralf Schledz, Martin Streibl, and Juergen Zielbauer, Cascading Techniques for a High-Speed Memory Interface, Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 2007, ISSCC 2007, Feb. 13, 2007, pp. 234-599.
Brent Keeth, R. Jacob Baker, DRAM Circuit Design, A Tutorial, IEEE Press Series on Microelectronic Systems, ISBN 0780360141, Nov. 2000, pp. 142-153, Wiley-IEEE Press, New York.

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