Memory device and memory error correction method

Details Memory device and memory error correction method Memory device and memory error correction method

2004-05-13

2008-11-04

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

C714S718000, C714S754000, C714S768000, C365S200000, C365S201000

Reexamination Certificate

active

07447950

ABSTRACT:
In a memory system, an ECC circuit is not inserted on a data path for data writing/reading. The ECC process is performed during the cycle of normal data reading/writing process, in such timing that it does not conflict with the data reading/writing process in order not to cause a substantial delay in the data writing/reading process. Specifically, the ECC process is performed during the cycle of burst transfer in which a plurality of data are successively input to or output from a shift register. Since no access is made to the memory cell array during the burst transfer cycle, the ECC process does not cause a delay in the reading/writing process.

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