Memory device and memory array

Details Memory device and memory array Memory device and memory array

1998-12-08

2000-10-17

Meier, Stephen D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257321, H01L 29788

Patent

active

061336033

ABSTRACT:
It is made possible to conduct writing and erasing information at high speed and with a low gate voltage, attain high integration with reduced power dissipation, and retain information accurately. It is also made possible to change the conductivity of a conduction layer efficiently depending on whether there are accumulated charges or not, even if the device is made finer. A barrier layer, a transition layer, a barrier layer, a transition layer, a barrier layer, a charge accumulation layer and a barrier layer are stacked one after another on a conduction layer to cause transition of charges in the conduction layer to the charge accumulation layer by resonance tunneling. In the conduction layer, one insulation portion and one insulation portion allowing charge tunneling are formed with the barrier layer in between. The capacitance of the insulation portions is made smaller than e.sup.2 /k.sub.B T (where e is the electric prime quantity, k.sub.B is the Boltzmann's constant, and T is operation temperature). The conduction layer, the transition layers, and the charge accumulation layer are made of Si. The barrier layers are made of SiO.sub.2 so that the electron affinity is made large, and small alternately.

REFERENCES:
patent: 5463235 (1995-10-01), Ishii
patent: 5604357 (1997-02-01), Hori

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