Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-07-31
2003-08-05
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S226000, C365S189090
Reexamination Certificate
active
06603698
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuits, and more specifically to refreshing dynamic data stored in an integrated circuit, such as a dynamic random access memory (DRAM), as a supply voltage applied to the integrated circuit varies.
BACKGROUND OF THE INVENTION
Many battery-powered portable electronic devices, such as laptop computers, Portable Digital Assistants, cell phones, and the like, require memory devices that provide large storage capacity and low power consumption. To reduce the power consumption and thereby extend the battery life in such devices, the devices typically operate in a low-power mode when the device is not being used. In the low-power mode, a supply voltage or voltages applied to electronic components such as a microprocessor, associated control chips, and memory devices are typically reduced to lower the power consumption of the components, as will be appreciated by those skilled in the art. Although the supply voltages are varied to reduce power consumption in the low-power mode, data stored in the electronic components such as the memory devices must be retained.
Because large storage capacity is typically desired to maximize the amount of available storage in portable devices, it is typically desirable to utilize dynamic random access memory (DRAM), which has a relatively large storage capacity, over other types of memories such as static random access memories (SRAM) and non-volatile memories such as FLASH memory. In a DRAM, the data is “dynamic” because the data stored in memory cells in the DRAM must be periodically recharged or “refreshed” to maintain the data, as will now be explained in more detail with reference to FIG.
1
.
FIG. 1
illustrates a portion of a conventional DRAM memory-cell array
100
including a plurality of memory cells
102
arranged in rows and columns, one of which is shown in FIG.
1
. The memory cell
102
includes an access transistor
104
and a storage capacitor
106
connected in series between a digit line DL and a reference voltage VCC/2. The storage capacitor
106
includes a first conductive plate
107
coupled to the access transistor
104
and a second conductive plate
109
coupled to the reference voltage VCC/2.
A word line WL activates the access transistor
104
in the memory cell
102
, and also activates the access transistors of all other memory cells (not shown) contained in the same row of the array
100
as the memory cell
102
. To write data into the memory cell
102
, a sense amplifier
108
drives the digit line DL and a complementary digit line DL*to complementary voltage levels corresponding to the data to be stored in the memory cell. The word line WL is then activated, turning ON the access transistor
104
and transferring charge through the access transistor to charge the storage capacitor
106
to the voltage level on the digit line DL corresponding to the data to be stored. The word line WL is thereafter deactivated, turning OFF the access transistor
104
and isolating the storage capacitor
106
from the digit line DL to thereby store the data in the form of a voltage across the storage capacitor.
To read data from the memory cell
102
, the sense amplifier
108
equilibrates the digit lines DL, DL* to a predetermined voltage level and thereafter activates the word line WL to turn ON the access transistor
104
. In response to the access transistor
104
turning ON, charge is transferred between the storage capacitor
106
and the digit line DL, causing the voltage on the digit line DL to be slightly higher or lower than the voltage on the digit line DL*. The sense amplifier
108
senses the difference between the voltages on the digit lines DL and DL* and drives the voltages on the digit lines to complementary levels in response to the sensed difference. For example, assume a voltage VCC/2 corresponding to a binary
1
is stored across the capacitor
106
. In this situation, when the access transistor
104
is activated the equilibrated voltage on the digit line DL will increase slightly relative to the equilibrated voltage on the digit line DL*. As a result, the sense amplifier
108
will drive the voltage on the digit line DL to a supply voltage VCC and will drive the complementary digit line DL* to a reference voltage. The complementary voltages on the digit lines DL, DL* thus correspond to the data stored in the memory cell
102
, and the sense amplifier
108
thereafter applies these signals to other circuitry (not shown) to thereby provide the circuitry with the data stored in the memory cell.
As previously mentioned, the data stored in the memory cell
102
in the form of the voltage across the capacitor
106
must be periodically refreshed. This is true because once the data is stored in the form of a voltage across the capacitor
106
and the access transistor
104
is deactivated, leakage currents ILK result in this stored voltage changing over time and, if not refreshed, may result in a different binary state of data being stored in the memory cell. These leakage currents ILK arise, for example, from the flow of charge stored on the conductive plate
107
of the capacitor
106
through the access transistor
104
even when the access transistor is turned OFF, and may also arise from the flow of charge from the conductive plates
107
,
109
to ground, as well as the flow of charge from the plate
107
through a dielectric (not shown) to the plate
109
, as will be appreciated by those skilled in the art. From the above description of the conventional DRAM memory cell
102
, it is seen that each time data is read from the memory cell the storage capacitor
106
is again charged to the proper voltage corresponding to the data stored in the cell. Thus, to refresh memory cells
102
, the memory cells are merely accessed as in a read operation with the sense amplifier
108
driving digit lines DL, DL* to complementary voltages corresponding to the data stored in the memory cell and thereby charging the storage capacitors
106
to the proper voltage.
The rate at which the data restored in the memory cells
102
must be periodically refreshed is known as the refresh rate of the cells, and is a function of a number of different parameters, including the operating temperature of the DRAM containing the array
100
, the number of rows of memory cells in the array, and the value of the supply voltage VCC applied to the DRAM, as will be appreciated by those skilled in the art. For example, if the array
100
includes N rows of memory cells
102
and each memory cell must be refreshed every M milliseconds, the refresh rate is MIN milliseconds/row, meaning that one row must be accessed every M/N milliseconds in order to properly refresh the memory cells, with every row being accessed at least once every M milliseconds. As the supply voltage VCC decreases, the refresh rate increases due, for example, to a reduced voltage being stored across the storage capacitors
106
and the need to refresh this voltage more frequently to ensure the stored voltage does not decay to an insufficient level due to the leakage currents ILK. The refresh rate also must increase as the supply voltage VCC decreases due to the possibility of restoring incorrect data into the memory cell
102
, as will be appreciated by those skilled in the art.
When the memory-cell array
100
is contained in a DRAM, a memory controller typically reads data from desired memory cells
102
in response to requests from a microprocessor or other control circuit, each accessed memory cell being automatically refreshed as previously described. The data stored in all the memory cells
102
and not just those accessed by the memory controller, however, must be periodically refreshed. As a result, during normal operation the memory controller will periodically apply a refresh command to the DRAM containing the array
100
, causing control circuitry (not shown) to access each memory cell
102
as previously described and thereby refreshing the memory cells. Even when the memory controller is not acces
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