Memory device and a method for prohibiting writing to the memory

Static information storage and retrieval – Read/write circuit – Signals

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36518701, G11C 700

Patent

active

053553365

ABSTRACT:
A memory device connected to a CPU and including a plurality of memory elements selectable between a writable state and an unwritable state, the CPU outputting an address signal for selecting at least one of the plurality of memory elements, data to be stored in the plurality of memory elements, and a write signal for selecting the writable state or the unwritable state of the plurality of memory elements to the memory device. The memory device includes an address decoder element for generating at least two select signals in response to the address signal; a first memory for storing first data outputted from the CPU in response to a first state select signal having a specified level for selecting the writable state or the unwritable state when a first two select signal is at a specified level; a second memory for storing and outputting second data outputted from the CPU in response to a second state select signal having a specified level for selecting the writable state or the unwritable state when a second select signal is at a specified level, the second data putting the first and the second memories into the unwritable state; and a logic operation element for performing logic operations of the write signal and the second data outputted from the second memory and outputting signals indicating results of the logic operations to the first and the second memories respectively. These signals are the first and the second state select signals.

REFERENCES:
patent: 4580246 (1986-04-01), Sibigtroth
patent: 4665506 (1987-05-01), Cline et al.
patent: 4975878 (1990-12-01), Boddu et al.
patent: 5016219 (1991-05-01), Nolan et al.
patent: 5047982 (1991-09-01), Smith et al.
patent: 5161122 (1992-11-01), Robertson

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