Memory device

Details Memory device Memory device

2002-12-03

2004-11-09

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06816398

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more specifically, it relates to a memory device storing data.
2. Description of the Background Art
A ferroelectric memory storing data through polarization of a ferroelectric substance is known in general. This ferroelectric memory is watched with interest as a high-speed nonvolatile memory requiring low power consumption. Therefore, the ferroelectric memory is actively researched and developed. A storage capacitance ferroelectric memory writing/reading data in a system similar to that of a DRAM (dynamic random access memory) employs one of two types of representative memory cells, i.e., a one-transistor two-capacitor (hereinafter referred to as
1
T
1
C) memory cell and a two-transistor two-capacitor (hereinafter referred to as
2
T
2
C) memory cell. The
2
T
2
C memory cell is disclosed in “Low-power High-speed LSI Circuits & Technology”, Jan. 31, 1998, pp. 235-245, for example.
FIG. 36
is a circuit diagram showing a memory cell part of a conventional
1
T
1
C ferroelectric memory.
FIG. 37
is a circuit diagram for illustrating a method of reading data in the conventional
1
T
1
C ferroelectric memory including memory cells and reference cells.
As shown in
FIG. 36
, each memory cell
103
of the conventional
1
T
1
C ferroelectric memory is formed by a selection transistor
101
and a ferroelectric capacitor
102
, similarly to that of a DRAM. When the selection transistor
101
is turned on in a reading operation of the ferroelectric memory, the ferroelectric capacitor
102
is connected with a bit line capacitor Cbl. Then, a plate line PL is pulse-driven to transmit charges varying with the direction of polarization of the ferroelectric capacitor
102
to a bit line BLT. Thus, the ferroelectric memory reads data as the voltage of the bit line BLT, similarly to the DRAM. Whether the data is “1” or “0” depends on the direction of polarization of the ferroelectric capacitor
102
. In this case, a reference cell is required for discharging charges in an intermediate quantity between those of charges discharged by the data “1” and “0” in data reading.
More specifically, reference cells
103
a
are connected to a pair of bit lines BLT and BLB respectively, as shown in FIG.
37
. The data read operation is now described in detail with reference to FIG.
37
. First, the pair of bit lines BLT and BLB are precharged to 0 V. When a word line WL
1
selects a memory cell
103
connected with the bit line BLT, a word line RefWLB selects the reference cell
103
a
connected with the bit line BLB. When a word line WL
2
selects a memory cell
103
connected with the bit line BLB, a word line RefWLT selects the reference cell
103
a
connected with the bit line BLT. Thereafter the plate line PL is pulse-driven so that charges corresponding to the memory cells
103
and the reference cells
103
a
are discharged to the pair of bit lines BLT and BLB. Thus, the pair of bit lines BLT and BLB obtain data signals of “1” or “0”. A sense amplifier
105
amplifies the difference between the potentials of the signals. Thus, the ferroelectric memory reads data.
FIG. 38
is a circuit diagram showing a memory cell part of a conventional
2
T
2
C ferroelectric memory. As shown in
FIG. 38
, two transistors and two capacitors are connected to a pair of bit lines BLT and BLB in the memory cell part of the
2
T
2
C ferroelectric memory. The two transistors and the two capacitors store complementary data as 1-bit data. In this case, no reference cells are required for preparing reference voltages for reading the complementary data, dissimilarly to the aforementioned
1
T
1
C ferroelectric memory.
In general, a matrix storage capacitance ferroelectric memory is also proposed.
FIG. 39
is a circuit diagram showing memory cells
121
of a conventional matrix ferroelectric memory. As shown in
FIG. 39
, ferroelectric capacitors
122
are arranged on intersections between word lines WL
1
to WL
4
and bit lines BL
1
to BL
4
in the memory cells
121
of the conventional matrix ferroelectric memory. The matrix ferroelectric memory, reading voltages through capacitive coupling between the bit lines BL
1
to BL
4
and the ferroelectric capacitors
122
, must ensure the capacitance similarly to the
1
T
1
C ferroelectric memory. In the matrix ferroelectric memory, each memory cell
121
is formed by only a single ferroelectric capacitor
122
, whereby the degree of integration can be more improved as compared with the
1
T
1
C ferroelectric memory.
FIG. 40
is a schematic diagram for illustrating the operation principle of the matrix ferroelectric memory shown in FIG.
39
. Operations of the conventional matrix ferroelectric memory are now described with reference to
FIGS. 39 and 40
.
First, each ferroelectric capacitor
122
has first and second ends connected to each word line WL and each bit line BL respectively. Both ends of the ferroelectric capacitor
122
are at the same potential in a standby state. In order to write data “1”, voltages of Vcc and 0 V are applied to the word line WL and the bit line BL respectively. At this time, the voltage Vcc is applied to the ferroelectric capacitor
122
. Thus, the ferroelectric capacitor
122
shifts to a point A in
FIG. 40
despite an initial state. When both ends of the ferroelectric capacitor
122
are thereafter set to the same potential, the ferroelectric capacitor
122
makes transition to “1” in FIG.
40
. In order to write data “0”, voltages of 0 V and Vcc are applied to the word line WL and the bit line BL respectively. At this time, a voltage −Vcc is applied to the ferroelectric capacitor
122
. Thus, the ferroelectric capacitor
122
shifts to a point B in FIG.
40
. When both ends of the ferroelectric capacitor
122
are thereafter set to the same potential, the ferroelectric capacitor
122
makes transition to “0” in FIG.
40
.
In a read operation, the bit line BL is precharged to 0 V. Then, the word line WL is set to the voltage Vcc. Assuming that Ccell represents the capacitance of the ferroelectric capacitor
122
of each memory cell, Cref represents the capacitance of a ferroelectric capacitor
122
a
of each reference cell
121
a
(see FIG.
39
), Cbl represents the parasitic capacitance of a bit line BLn and Cblref represents the parasitic capacitance of a reference bit line Blref, the voltage Vcc of the word line WL is capacitively divided by the capacitances Ccell and Cbl as to the bit line BLn, and capacitively divided by the parasitic capacitances Cref and Cblref as to the reference bit line Blref. The capacitance Ccell can be approximated as a capacitance C
0
or C
1
depending on held data. Therefore, a potential V
0
of the bit line BLn holding data “0”, a potential V
1
of the bit line BLn holding the data “1” and a potential Vref of the reference bit line Blref are expressed as follows respectively:
V
0
={
C
0
/(
C
0
+
Cbl
)}×
Vcc
  (1)
V
1
={
C
1
/(
C
1
+
Cbl
)}×
Vcc
  (2)
Vref=
{(
Cref
/(
Cref+Cblref
))×
Vcc
  (3)
The potential Vref of the reference bit line Blref is set to an intermediate level between the potential V
0
of the bit line BLn holding the data “0” and the potential V
1
of the bit line BLn holding the data “1”.
A sense amplifier determines the difference between the potential V
0
or V
1
and the potential Vref thereby performing reading. At this time, data of the memory cell is destroyed and hence a write operation (restoration) responsive to the read data is performed after the reading.
The conventional
1
T
1
C ferroelectric memory shown in
FIG. 36
having the memory cells each formed by only a single transistor and a single capacitor advantageously has a high degree of integration. However, a reference voltage disadvantageously deviates from a design value due to fabrication dispersion of the ferroelectric capacitor
102
of change of the quantity of polarization charges in the write and read

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