Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2002-05-20
2004-12-07
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S189070
Reexamination Certificate
active
06829187
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to memory devices that include a multiplicity of memory cells for storing data, and a read amplifier enabling the content of the relevant memory cell to be determined by evaluating the magnitude and/or the direction of a current flowing between this cell and the read amplifier during a read-out of the memory cell. In addition, or alternatively, the memory device can include a decoding device exhibiting two or more mutually cooperating decoding units for selecting the memory cell(s) to be read out or to be written to.
Memory devices of this type are, in particular, semiconductor memories such as, for example, RAMs (Random Access Memories), ROMs (Read Only Memories), EPROMs (Erasable Programmable Read Only Memories), EEPROMs (Electrically Erasable Programmable Read Only Memories), and flash memories etc. Such memory devices have been known for many years in numerous embodiments and do not need to be explained in greater detail.
As much as possible, such memory devices and other memory devices are needed to operate at an increasingly faster rate and at the same time to require less and less chip area and consume less and less energy.
To this end, among other things, various improvements in the decoding device provided for selecting the memory cell(s) to be read out or to be written to and improvements in the read amplifier provided for determining the memory cell contents have already been made.
The improvements in the decoding device consist of providing the decoding device, or more precisely the part of it used for selecting memory cell rows, with a so-called pre-decoder and a multiplicity of so-called post-decoders. The pre-decoder carries out a pre-decoding in which it is “only” determined in which memory cell row area (including a number of memory cell rows), the memory cells to be read out or to be written to are located. The post-decoders, which follow the pre-decoder and which in each case are allocated to a particular memory cell row area, determine the particular memory cell row in which the memory cells to be read out or to be written to are located. Such structuring of the decoding device allows the required chip area to be reduced and allows the performance of the decoding device to be enhanced.
The improvements in the read amplifier consist of, among other things, no longer determining the content of a memory cell to be read out on the basis of the voltage that occurs on the bit line during the read-out of the relevant memory cell, but on the basis of the magnitude and/or the direction of the current that occurs between this cell and the read amplifier during the read-out of the relevant memory cell. A determination of the memory cell content based on power flow can be performed more rapidly and with less energy consumption than is the case with a determination based on the voltage.
Due to the aforementioned measures, it was possible to develop chips that are smaller, that manage with less energy, and that operate at a faster rate than was previously the case.
In the meantime, however, it has been found that this is not always the case. Under certain circumstances, the aforementioned advantages cannot be achieved and/or memory chips constructed as described operate unreliably or incorrectly.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory device which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide a memory device that they can be implemented to be small under all circumstances, that requires little energy, and that operates reliably and at a rapid rate.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory device, including: a plurality of memory cells for storing data; and a read amplifier for determining the data of a relevant one of the plurality of the memory cells by evaluating a characteristic of a current flowing between the relevant one of the plurality of the memory cells and the read amplifier. The characteristic is either a magnitude of the current or a direction of the current. The read amplifier having a variable input impedance.
In accordance with an added feature of the invention, the read amplifier has components with dimensions; and the input impedance of the read amplifier can be varied by varying the dimensions of selected ones of the components of the read amplifier.
In accordance with an additional feature of the invention, the read amplifier has components; the read amplifier has a drive for selected ones of the components; and the input impedance of the read amplifier can be varied by varying the drive.
In accordance with another feature of the invention, the read amplifier includes an input and a symmetrically constructed amplifier stage having two identically configured amplifier branches connected to the input.
In accordance with a further feature of the invention, each one of the amplifier branches has a transistor operated in a common-gate configuration and a load resistor following the transistor.
In accordance with a further added feature of the invention, each one of the amplifier branches includes an input and a transistor connecting the input to ground.
In accordance with a further additional feature of the invention, further amplifier branches are constructed complementary to each other. Each one of the further amplifier branches is connected in parallel with a respective one of the amplifier branches at the input.
In accordance with yet an added feature of the invention, the read amplifier includes an input and an asymmetrically constructed amplifier stage having two complementary configured amplifier branches connected to the input.
In accordance with yet an additional feature of the invention, the read amplifier includes an input and an asymmetrically constructed amplifier stage having only one amplifier branch connected to the input.
In accordance with yet another feature of the invention, a further amplifier branch is constructed complementary to the amplifier branch. The further amplifier branch is connected in parallel with the amplifier branch at the input.
In accordance with yet a further feature of the invention, the transistor in each one of the amplifier branches has a gate terminal receiving a voltage acting to vary the input impedance of the read amplifier.
In accordance with yet a further added feature of the invention, the read amplifier has adjustable components; and the voltage applied to the gate terminal of the transistor in each one of the amplifier branches can be varied by adjusting the adjustable components.
In accordance with yet a further additional feature of the invention, coupling branches are provided. Each one of the coupling branches provides a voltage from one of the amplifier branches. The gate terminal of the transistor in each one of the amplifier branches receives the voltage from a respective one of the coupling branches.
In accordance with an added feature of the invention, a voltage divider providing voltages and coupling branches are provided. The transistor in each one of the amplifier branches has a gate terminal. The coupling branches apply a respective one of the voltages from the voltage divider to the gates terminals of the transistors in the amplifier branches.
In accordance with an additional feature of the invention, the load resistor is formed by a CMOS voltage divider.
In accordance with another feature of the invention, the voltage divider is formed by a CMOS voltage divider.
In accordance with a further feature of the invention, the load resistor is constructed to provide various voltages.
In accordance with a further added feature of the invention, the load resistor is formed by a resistor that can be tapped at a plurality of points.
In accordance with a further additional feature of the invention, the load resistor is formed by a diode-connected transistor and a transistor that forms a load resistor;
Paul Steffen
Seifert Martin
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Tran M.
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