Memory device

Details Memory device Memory device

2001-04-04

2004-01-13

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

06678789

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device which comprises a storage buffer and a cache memory, and more particularly relates to a memory device designed to achieve enhanced performance and reduced electrical power consumption.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 37 CFR 1.98
In conventional microprocessors, in order to increase the speed of data access to main memory which is of high capacity but low speed, the microprocessors have been widely practiced of providing a cache memory which is of low capacity but high speed, thereby suppressing data access latency. In particular, in recent years, the difference between the processing speed of the microprocessor and the external processing speed of the chips in the main memory etc. has gradually become remarkable, and the tendency has been to include a cache memory of greater and greater capacity in the processor.
Further, with programs which consume large quantities of data such as involved in multimedia processing, a cache memory with a large number of ports is provided, since the cache memory is required to supply a large quantity of data at one time, and microprocessors have also become more common which are capable of simultaneously processing access by a plurality of load commands or store commands, and of simultaneously processing access by a load command or a store command and data transfer between the main memory and the cache memory. In implementing such a multi-port cache memory, the cost upon the layout area is high if the memory cells themselves are made as multi-port. For this reason the cache memory is normally divided into smaller units, termed banks, and a bank interleave method is adopted for simultaneously processing accesses to each bank. In this case, it becomes possible to process accesses to different banks simultaneously.
Normally, when a load command has been issued to a cache memory such as described above, processing is completed in a single pipeline stage, because cache tag reading out and hit decision, and reading out of cache data, are performed in parallel. On the other hand, when a store command has been issued, the data only comes to be actually written after the cache tag reading out and the hit decision have been performed, and it has been determined whether or not writing is possible and the cache way for which writing should be performed. Due to this, more processing time is taken for a store command than for a load command, and in general two or more pipeline stages are required. As a result, when a store command and a load command have been issued in sequence, the processing speed undesirably drops because the pipeline timings of accesses to the cache memory do not properly agree.
In order to solve the above problem, there is a type of microprocessor which, as well as having a cache memory, is equipped with a so called storage buffer which contains the store data due to store commands. In a microprocessor equipped with such a storage buffer, store data due to a store command is temporarily stored in the storage buffer, and pipeline timing adjustment for load commands and store commands becomes possible due to writing being performed from the storage buffer into the cache memory, so that it is possible to ensure good processing speed even for store commands.
Further, with a microprocessor equipped with the above described storage buffer, efficiency is attained even for speculative store commands due to branch commands or the like.
For example, in recent years the practice of performing speculative execution of commands based upon a branch forecast mechanism has become widespread, in order to execute pipeline operation for branch commands smoothly. In this branch forecast mechanism the destination of the branch is forecast, and the commands at the forecast destination of the branch are speculatively executed before the address of the destination of the branch is actually determined.
In this case, it is necessary to cancel the commands which have been speculatively executed when the forecast for the branch destination proves to be mistaken. However, it is not easy to cancel the result of a store command which has been written into the cache memory. By contrast, it is easy to cancel the result of a store command which has been written into the storage buffer. Accordingly the data stored by a speculative store command is temporarily stored in the storage buffer, and is only written into the cache memory from the storage buffer after it has been verified that the branch forecast has succeeded, while if the branch forecast proves to be mistaken it is sufficient to perform cancellation of this data stored by the speculative store command in the storage buffer. By doing this, it becomes possible to forecast the destination of the branch before the destination of the branch is actually verified, and speculatively to execute the commands at the forecast destination of the branch which include the store command.
Further, the store data which is stored in the storage buffer is the most recent data. Due to this, for subsequent load commands for the same address, it becomes possible to read out this data from the storage buffer, rather than from the main memory or the cache memory. Normally the storage buffer is equipped with a mechanism which presents to subsequent load commands the store data which have been stored in the storage buffer. Further, if a plurality of store commands have been issued for the same address, it is necessary to protect the store data for the earlier store commands in the storage buffer so that they are not destroyed by the store data for the subsequent store commands. For this reason, such a storage buffer is usually implemented as a first-in first-out (FIFO) buffer, and is controlled so that writing into the cache memory is performed in order from the store data of the store command which was issued first. Moreover, details of such storage buffers are disclosed, for example, in Japanese Unexamined Patent Applications, First Publication Nos. Hei 6-301600 and Hei 8-36491.
As described above, in application to a portable information terminal or the like, on the one hand the demands upon the microprocessor for reduction of electrical power consumption are becoming more and more strident, and on the other hand there is the problem that the proportion of the consumption of electrical power by the microprocessor due to the cache memory becomes greater, because of elevation of the operating frequency and increase of the capacity of the cache memory and increase in the number of its ports and the like.
Further, if the number of access requests to the cache memory which are simultaneously generated is greater than the number of ports possessed by the cache memory, then, since it becomes necessary to compel one or more of these accesses to wait until a port becomes free, there is the problem that the processing performance is to this extent deteriorated.
Yet further, when implementing a multi-port cache memory according to the bank-interleave method, when so-called bank conflict is generated in which several attempts are made to access the same bank simultaneously, then, since it becomes necessary to process these accesses one at a time in order, there is the problem that the processing performance is to this extent deteriorated.
BRIEF SUMMARY OF THE INVENTION
In light of the above problem, an object of the present invention is to provide a memory device which, along with reducing the electrical power consumption due to the cache memory, also reduces the proportion of port conflicts and bank conflicts which occur, thus alleviating the reduction of processing capability entailed thereby.
In order to attain the above-mentioned object, the present invention provides a memory device which comprises a storage buffer which temporarily maintains store data for a cache memory or a main memory, and in which, if load data has been read out from said cache memory by a load command, said load dat

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