Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-05-30
2002-12-24
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06498742
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device for data storage and in particular the invention relates to a memory device which makes use of ferroelectric materials for data storage.
2. Description of the Related Art
Ferroelectric materials can exhibit a non-volatile, bi-stable internal polarisation. The state of polarisation is established by the application of a voltage between opposing surfaces of the material. Having applied a sufficiently large voltage to internally polarise the material, it is subsequently possible to determine the direction of polarisation—which can be used as a binary indicator, whereby the material can act as a data storage medium. However, a problem arises in that the data read operation is destructive of the data. Specifically, the read operation consists of applying a voltage to set the polarisation in a specified direction. If the polarisation is already in that direction no charge exchange is required. However, if the polarisation is in the opposite direction a relatively large amount of charge exchange is required to establish the specified direction of polarisation. Thus, the previous direction of polarisation can be judged according to the high or low (zero) level of charge exchange required to establish the specified polarisation.
A ferroelectric data storage device in which the stored data can be read non-destructively is possible by detecting the polarisation of the ferroelectric material using the field effect. Specifically, using a ferroelectric material in place of the conventional gate oxide layer in a field effect transistor results in a detectable hysterisis in the transfer characteristic of the transistor. This device may conveniently be referred to as a ferroelectric field effect transistor, or FFET. Such a device is very attractive for many applications but it's widespread adoption is hindered by several problems. Firstly, high power consumption occurs during the read operation when the channel of the transistor is in the on state. Secondly, a high voltage is required to write data (switch polarisation direction) when the channel is in the off state.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory device which makes use of the internal polarisation of a ferroelectric material for data storage and in which a non-destructive data read operation can be undertaken. It is an object of one aspect of the present invention to avoid high power consumption during the read operation. It is an object of another aspect of the present invention to avoid the need for a high write voltage during the write operation.
According to a first aspect of the present invention there is provided a memory device comprising a single substrate having an n-type transistor and p-type transistor formed therein; the n-type transistor having an n-type source and an n-type drain; the p-type transistor having a p-type source and a p-type drain; both transistors sharing a single, common channel region and a single, common gate electrode located above the channel region; the source and drains of the transistors being connected in series between the two transistors; and a single, common ferroelectric material separating the gate from the channel.
Preferably, the channel region has intrinsic doping only.
Preferably, the each of the n-type source, the n-type drain, the p-type source and the p-type drain has a region of reduced doping so as to reduce leakage currents between the two transistors.
According to a second aspect of the present invention there is provided a method of reducing power consumption in a memory device which stores data using the polarisation of a ferroelectric material comprising the steps of: providing an n-type transistor and p-type transistor formed in a single substrate with the n-type transistor having an n-type source and an n-type drain and the p-type transistor having a p-type source and a p-type drain; providing a single, common channel region and a single common gate electrode located above the channel region; arranging for the source and drains of the transistors to be connected in series between the two transistors; and providing a single, common ferroelectric material separating the gate from the channel.
Preferably, the method comprises the step of arranging for the channel region to have intrinsic doping only.
Preferably, the method comprises the step of providing each of the n-type source, the n-type drain, the p-type source and the p-type drain with a respective region of reduced doping so as to reduce leakage currents between the two transistors.
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patent: 5361224 (1994-11-01), Takasu
patent: 5535154 (1996-07-01), Kiyono
patent: 5559733 (1996-09-01), McMillan et al.
patent: 5923184 (1999-07-01), Ooms et al.
patent: 6233169 (2001-05-01), Nishimura
patent: 6314016 (2001-11-01), Takasu
Oliff & Berridg,e PLC
Phan Trong
Seiko Epson Corporation
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