Memory device

Details Memory device Memory device

2000-03-10

2001-01-30

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S194000

Reexamination Certificate

active

06181637

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a memory device of which the activation timing of the sense amp is adequately controlled.
2. Description of the Prior Art
FIG. 9
is an outline drawing of a prior art memory device. The prior art memory device comprises a memory cell
5
in which an NMOS transistor
7
and capacitor
8
are located at the point of intersection of a word line WL and bit line BL, a word-line driver
4
which activates the word line WL in response to a row address strobe ras (row activation signal), a sense amp
3
which reads and amplifies the electric potential difference between the bit line BL,/BL during reading and writing of the memory cell, a delay circuit
1
which applies a specified delay time to the row address strobe ras, and generates a latch-enable signal le, a sense-amp activation circuit
2
which generates sense-amp activation signals lepx, lenz from the latch-enable signal le, and a boost-up circuit
6
which generates a boosted power-supply voltage Vpp from an external power-supply voltage Vdd.
When a row address strobe ras is input to the wordline driver
4
from the CPU or memory controller (not shown in the figure), the potential of the word line WL rises, the NMOS transistor
7
begins to conduct, and voltage corresponding to the data held in the capacitor
8
is applied to the bit line BL.
Next, the sense-amp activation signals lepx, lenz are output at the timing of the occurrence of a very small potential difference between the bit lines BL,/BL, and the sense amp
3
is activated. The sense amp
3
reads and amplifies the potential difference between the bit lines BL,/BL.
FIG. 10
is a schematic drawing of a delay circuit
1
in a prior art memory device. The delay circuit
1
comprises inverters
46
,
47
,
49
,
52
,
54
,
61
,
62
, a NOR circuit
51
and capacitors
48
,
50
,
53
,
55
, and an external power-supply voltage Vdd is supplied as the driving power-supply of the inverters
46
,
47
,
49
,
52
,
54
,
61
,
62
and NOR circuit
51
.
The delay time of the delay circuit
1
is set to a value such that an interval (WL-LE) can be maintained between the activation timing of word line WL and the activation timing of the sense amp
3
. In this way it is possible to activate the sense amp
3
at proper timing when the small potential difference occurs between the bit lines BL,/BL.
FIG. 11
is a timing chart of the operation of the delay circuit
1
. When the row address strobe ras becomes high, the word-line driver
4
is activated as described above, and the potential of the word line WL rises. On the other hand, the row address strobe ras is inverted by the inverter
46
in the delay circuit
1
, and becomes the signal at node n1, and a delay of time t1 is applied by inverters
47
,
49
and capacitors
48
,
50
to become the signal at node n2.
The signal at node n1 and the signal at node n2 are input to the NOR circuit
51
and become the signal at node n3, and a further delay of time t2 is applied by inverters
52
,
54
and capacitors
53
,
55
to become the signal at node n4. The waveform of the signal at node n4 is shaped by inverters
61
,
62
to become the latch-enable signal le. When the level of this latch-enable signal le becomes high, the sense amp
3
is activated. The delay time of the delay circuit
1
in this case is (t1+t2).
FIG. 12
shows the waveform of the memory cell
5
during operation under normal conditions when the external power-supply voltage Vdd is less than the boosted power-supply voltage Vpp. When the row address strobe ras is input, the potential of the word line WL rises. The boosted power-supply voltage Vpp is applied to the word line WL, so the potential of the word line WL rises at a slope that corresponds to the voltage level of the boosted power-supply voltage Vpp.
When the potential of the word line WL rises, the NMOS transistor
7
of the memory cell
5
begins to conduct, and the charge of the capacitor
8
is discharged to the bit line BL. The change in the charging voltage of the capacitor
8
is shown by the dotted line. A potential difference begins to occur between the bit lines BL,/BL as the charge is discharged from the capacitor
8
.
After the potential of the word line WL has risen, the delay time (t1+t2) of the delay circuit
1
is set to correspond with time required for a potential difference, that can be amplified by the sense amp
3
, to occur in the bit lines BL,/BL. This time is the aforementioned interval WL-LE.
At the timing when there is a sufficient potential difference in the bit lines BL,/BL, the sense-amp activation signals lepx, lenz are input to the sense amp, and the sense amp reads and amplifies the potential difference in the bit lines BL,/BL. Since the external power-supply voltage Vdd is applied to the delay circuit
1
, the delay time (t1+t2) of the delay circuit
1
changes depending on the external power-supply voltage Vdd.
As described above, the boosted power-supply voltage Vpp that raised the external power-supply voltage Vdd is applied to the word line driver
4
, and the word line WL is driven by the boosted power-supply voltage Vpp. This is done in order that high voltage is applied to the gate of the NMOS transistor
7
of the memory cell
5
so that the NMOS transistor
7
conducts sufficiently. Moreover, in order to reduce the power consumed, the cell step-down power-supply voltage Viic that is lowered from the external power-supply voltage Vdd is applied to the memory cell
5
by way of the sense amp.
When this happens, the boosted power-supply voltage Vpp or the cell step-down power-supply voltage Viic is the constant voltage that is generated inside the memory device so the effect due to fluctuations of the external power-supply voltage Vdd is small. Also, since the necessary WL-LE interval for memory operation is determined by the voltage level of the boosted power-supply voltage Vpp and cell step-down power-supply voltage Viic, it does not change even if the external power-supply voltage changes.
On the other hand, the external power-supply voltage Vdd is supplied to the delay circuit
1
as shown in FIG.
10
. There are two main reasons that the external power-supply voltage Vdd is used as the power supply for the delay circuit
1
instead of the boosted power-supply voltage Vpp.
(1) The converting efficiency of the boost-up circuit
6
that generates the boosted power-supply voltage Vpp from the external power-supply voltage Vdd is 30 to 50%, and since it consumes more power than the amount supplied to the load side, from the aspect of lowering the power consumption, it is necessary to restrict the destination to which the boosted power-supply voltage Vpp is supplied.
(2) Constantly applying a high voltage, such as the boosted power supply voltage Vpp, to components of the delay circuit
1
such as the inverter
46
, shortens the life of components such as the inverter
46
due to the large stress voltage, and so it is not desirable.
The external power-supply voltage Vdd is supplied to the delay circuit
1
in the prior art because of the above reasons. In this case, the voltage level of the external power-supply voltage Vdd easily changes depending on the model of external power supply used, and when the external power-supply voltage Vdd changes to become high, the slope of the signal amplitude of the inverter
46
becomes steep and the delay time (t1+t2) of the delay circuit
1
becomes short.
FIG. 13
shows the operating waveform of the memory cell
5
when the external power-supply voltage Vdd becomes larger than the boosted power-supply voltage Vpp. As shown in
FIG. 13
, when the external power-supply voltage Vdd is set to be high, the delay time (t1+t2) of the delay circuit
1
becomes short, and the output timing of the sense amp activation signals lepx, lenz becomes faster and the WL-LE interval becomes shorter. When this happens, the sense amp
3
is activated before enough potential difference can be generated between the bit lines BL,/BL, and so the m

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