Memory device

Details Memory device Memory device

2000-02-11

2001-05-01

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

C365S189030, C365S189040, C365S189050, C365S205000

Reexamination Certificate

active

06226203

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device such as DRAM, and more particularly to a memory device comprising a common data bus for a plurality of segments that increases the speed of write operations following reading or prevents reductions in reading speed due to noise during reading.
2. Description of the Related Art
Synchronous dynamic RAM (SDRAM) and the like are noteworthy as high speed DRAM. Increasing reading speeds is a very important requirement for such high speed DRAM. Also, it is necessary to increase the speed of write operations following read operations. The latest memory devices are not just individual memory devices; these new memory devices are proposed for the purposes of “RAM and logic” devices which are joined to logic circuits. Consequently the memory device disclosed in this specification may also be applied to such RAM and logic devices.
FIG. 1
shows the constitution of a conventional memory device. The memory device shown in
FIG. 1
comprises eight segments SGM
0
~
7
. Each of the segments comprises a plurality of memory cells and sense amps; each segment includes a column decoder C/Dec and four groups of read sense buffers SB and write amps WA. Within each segment, the abovementioned four groups of sense buffers SB and write amps WA are connected to four groups of memory cells selected with the column decoder C/Dec.
The four groups of sense buffers SB and write amps WA in segments SGM
0
~
3
are connected to the common data bus cdb
0
z~cdb
3
z, respectively, established in common for the four segments. The four groups of sense buffers SB and write amps WA in segments SGM
4
~
7
are likewise connected to the common data bus cdb
4
z~cdb
7
z established in common for the four segments. The sense buffer SB or write amp WA of one of the segments SGM
0
~
3
is activated and read data are output to the common data bus cdb
0
z~cdb
3
z or write data are supplied to the common data bus from a data input circuit, not shown. This is the same for segments SGM
4
~
7
.
The eight common data buses cdb
0
z~cdb
7
z are each connected to eight groups of data input circuits and data output circuits, not shown. Those data input circuits and output circuits are each connected to data input/output terminals (DQ terminals). Specifically, in the example in
FIG. 1
, 8 bits of data are output simultaneously in a read operation and 8 bits of data are input simultaneously in a write operation.
In a conventional memory device, there is a margin of time between the read operations and write operations; consequently, the common data buses established in common for a plurality of segments are used for both reading and writing.
However, further improvements are necessary in order to meet the requirements of higher speed memory devices. For example, when performing a write operation after reading, it is required that the write operation be at high speeds. Furthermore, disruption of the waveform due to coupling noise between data buses during reading sometimes causes reductions in reading speeds.
FIG. 2
is a timing chart for explaining the problems with the prior art.
FIG. 2A
shows the common data bus cdb#z in the case of a write command Write provided following a read command Read. In the case of synchronous DRAM (SDRAM), the control commands are supplied in synchronization with the leading edge of the clock CLK. In a usual read operation, an active command Active, not shown, is supplied; in response thereto, a wordline is driven, a sense amp is driven, and the voltage of the bitline is increased. After that, when a read command Read is supplied in synchronization with the leading edge of the clock CLK, the sense buffer SB is activated and the common data bus cdb#z connected thereto is driven according to the read data.
In
FIG. 2A
, once the read command Read is supplied, the common data bus cdb#z is driven and read data are output after one clock and read data are output to the data input/output terminal DQ, not shown, after two clocks. Specifically, the CAS latency, being the number of clocks from when the read command is input until data are output to the data input/output terminal DQ, is set to two.
However, when a write command Write
1
is supplied at the leading edge of the clock CLK directly following the read operation and at the same time, write data are supplied to the data input/output terminal DQ, not shown, the write data may be supplied to the common data bus cdb#z and cause an erroneous operation where read data are still being output to the common data bus cdb#z. In particular, a fight between the read data and write data on the abovementioned common data bus occurs when the operation frequency is increased by raising the frequency of the synchronizing clock CLK. Such a data conflict is thought to result from the difference between the time it takes for read data to move from the sense amp in the segment to the common data bus cdb#z, and the time it takes for write data to move from the data input/output terminal to the common data bus cdb#z. Consequently, in conventional memory devices, a write command following a read operation, like Write
2
in the figure, must be delayed by one clock.
Furthermore,
FIG. 2B
shows the decrease in reading speed due to coupling noise when the common data bus is driven in response to a read command. As shown in
FIG. 1
, the eight common data buses cdb#z are established beside each other. Consequently, when mutually different read data are supplied with the same timing to adjacent common data buses cdb
0
z, cdb
1
z by the sense buffers SB, it is sometimes the case that the level of the common data bus cdb
0
z, which is driven High, temporarily drops due to the coupling influence from the adjacent common data bus cdb
1
z which is driven Low and the time necessary for reaching the High level is delayed (&Dgr;t in the figure). At the same time, the level of the common data bus cdb
1
z which is driven Low temporarily rises due to the coupling influence from the adjacent common data bus cdb
0
z which is driven High, and the time necessary for reaching the Low level is delayed.
This read data delay &Dgr;t due to the coupling noise is a delay that brings about decreases in reading speeds overall, and in particular, should be prevented in order to keep the time until the read data are output within the catalog-specified values at high speed clocks CLK.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory device which can increase the speed of write operations after reading or during reading.
It is a further object of the present invention to provide a memory device which can raise reading speeds.
It is a further object of the present invention to provide a memory device comprising a new common data bus structure.
In order to achieve the abovementioned objects, it is a first aspect of the present invention to split a common data bus established in common for a plurality of segments into a read-dedicated common data bus and a write dedicated common data bus, in a memory device comprising a plurality of segments each of which includes a plurality of memory cells. With such a constitution, write data can be supplied to the write data bus even when read data are present on the read common data bus due to a read operation; and even when operation frequencies increase, there are no limitations to the timing of write operations following reading and the speed of write operations following reading can be increased.
In order to achieve the abovementioned objects, it is a second aspect of the present invention to split a common data bus into a read-dedicated common data bus and a write-dedicated common data bus as above, while alternately establishing the read common data bus and write common data bus. With such a constitution, a write common data bus is established between adjacent read common data buses and coupling noise due to the inverse read data is minimized even when different data are supplied on adjacent read commo

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