Memory device

Details Memory device Memory device

1996-10-25

1997-12-23

Dinh, Son T.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365193, 3652335, G11C 800

Patent

active

057012733

ABSTRACT:
A memory device comprising a cell array including first and second cell array blocks for storing data therein, an address buffer for generating an internal column address signal in response to an external column address signal and an internal column address strobe signal, a pre-decoder for pre-decoding the internal column address signal from the address buffer, a first latch circuit for generating a first internal column address signal in response to the pre-decoded internal column address signal from the pre-decoder and a first column address strobe signal, a second latch circuit for generating a second internal column address signal in response to the pre-decoded internal column address signal from the pre-decoder and a second column address strobe signal, a first column decoder for selectively driving bit lines to the first cell array block in response to the first internal column address signal from the first latch circuit to transfer external data to the first cell array block or to transfer data from the first cell array block externally, and a second column decoder for selectively driving bit lines to the second cell array block in response to the second internal column address signal from the second latch circuit to transfer external data to the second cell array block or to transfer data from the second cell array block externally.

REFERENCES:
patent: 5233565 (1993-08-01), Wang
patent: 5251181 (1993-10-01), Toda
patent: 5293347 (1994-03-01), Ogawa
patent: 5357479 (1994-10-01), Matsui
patent: 5544098 (1996-08-01), Matsuo et al.
patent: 5600606 (1997-02-01), Rao

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