Memory device

Details Memory device Memory device

1994-11-22

1996-07-16

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

36518912, 365149, G11C 700

Patent

active

055373593

ABSTRACT:
In a serial access memory device in which dynamic memory cells and serial registers are combined, the chip area occupied by the added serial registers can be reduced and thereby the cost of the memory chip can be reduced. The dynamic serial registers (SR) for reading data in series are provided in correspondence to the dynamic cell array (CA). When data are read under control of a transfer gate control block (X'fer CTL), the address is stored in an address compare block (X'fer Add). During the refresh of the cell array (CA) by a refresh control block (Ref CTL), the address of the cells being refreshed is given to the address compare block (X'fer Add). When both address match, the data of the cell array (CA) are transferred again to the serial registers (SR) through the transfer gate control block (X'fer CTL) to refresh the data of the serial registers.

REFERENCES:
patent: 4739500 (1988-04-01), Miyamoto
patent: 5053997 (1991-10-01), Miyamoto et al.

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