Memory device

Details Memory device Memory device

1981-10-05

1984-04-24

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Signals

365233, G11C 700

Patent

active

044452047

ABSTRACT:
A memory device provided with an improved control circuit for enabling effective interface with a CPU. The device comprises a memory circuit, a first terminal for receiving a strobe signal for placing the memory circuit in an accessed state, a second terminal for receiving a chain of clock signals, digital counter for counting the clock signals in response to the strobe signal having a plurality of different value of count, output terminals, a circuit for selectively deriving a count signal from one of the count output terminal according to a programmed state, and a ready signal generating circuit for generating a ready signal for indicating the completion of the access operation of the memory circuit in response to the count signal.

REFERENCES:
patent: 4090096 (1978-05-01), Nagami
patent: 4337523 (1982-06-01), Hotta et al.
Meadows et al., "Programmable Store Variation," IBM Tech. Disc. Bul., vol. 9, No. 10, 3/67, pp. 1399-1400.
Arzubi, "Encoded Variable Delay for Driver Circuits," IBM Tech. Disc. Bul., vol. 22, No. 2, 7/79, pp. 518-519.

Affiliated with

Also associated with

Rating

Memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-119168