Memory device

Details Memory device Memory device

1980-05-01

1982-06-08

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365182, G11C 1140

Patent

active

043342957

ABSTRACT:
A two-clock multi-address input dynamic random access memory provided with an internal refresh function for refreshing memory cells without receiving refresh address information from the outside is disclosed. The memory characteristically comprises a terminal for receiving a refresh control signal, refresh address means for designating a row address to be refreshed, means for producing confirmation signal when a reset precharge of a circuit relating to a refresh operation is completed, means for storing the refresh control signal when a row address strobe signal is in active level, and means responsive to the confirmation signal and the stored refresh signal for effecting the refresh operation.

REFERENCES:
patent: 3737879 (1973-06-01), Greene et al.

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