Memory device

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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Details

C365S203000, C365S207000

Reexamination Certificate

active

11069940

ABSTRACT:
A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.

REFERENCES:
patent: 5148063 (1992-09-01), Hotta
patent: 5771197 (1998-06-01), Kim
patent: 5886937 (1999-03-01), Jang
patent: RE36579 (2000-02-01), Pascucci et al.
patent: 6052307 (2000-04-01), Huber et al.
patent: 6069831 (2000-05-01), Jang et al.
patent: 6087859 (2000-07-01), Lee et al.
patent: 2002/0009009 (2002-01-01), Ahmed et al.
patent: 2002/0105831 (2002-08-01), Lee et al.
patent: 10-209304 (1998-08-01), None
patent: 10-261298 (1998-09-01), None
patent: 2002-237194 (2002-08-01), None

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