Memory design which facilitates incremental fetch and store requ

Details Memory design which facilitates incremental fetch and store requ Memory design which facilitates incremental fetch and store requ

1996-10-03

1999-06-08

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

711213, G06F 1206

Patent

active

059111534

ABSTRACT:
A memory design which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies extraneous control of typical requesters built into a memory system. The memory design also reduces power consumed by requests which exploit the memory's internal address generation facility. Power consumption is further reduced while maintaining memory access times by selectively gating data bits vital to the memory's logic flow at an earlier stage in the memory when the gating or steering address bits are known in advance of the data arriving to that stage.

REFERENCES:
patent: 5691956 (1997-11-01), Chang et al.
patent: 5783958 (1998-07-01), Lysinger
patent: 5784712 (1998-07-01), Byers et al.

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