Memory defragmentation in chipcards

Details Memory defragmentation in chipcards Memory defragmentation in chipcards

2007-01-23

2007-01-23

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S103000, C711S133000, C711S170000, C711S159000, C711S139000

Reexamination Certificate

active

09533731

ABSTRACT:
The basic idea comprised of the present invention is to provide two sets of descriptors having each at least three descriptors and each set is used in an alternating manner for defining the location of source and target of the copy operations which are to be performed during the defragmentation procedure. The defragmentation procedure is performed as a sequence of copy operations on copy chunks, i.e., a certain number of sequentially arranged bytes to be copied being part of a valid data block to be copied. In each of said copy operations in said sequence the values which are assigned to said descriptors Change. According to a characterizing feature of the present invention during the whole sequence of copy operations comprised of the defragmentation process one of the two sets of descriptors holds information which is usable for restoring the contents of a copy chunk in case of a power break during a copy operation on said copy chunk. Thus, defragmenting is a safe procedure, and data integrity is assured.

REFERENCES:
patent: 6038636 (2000-04-01), Brown, III et al.

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