Memory defect steering circuit

Details Memory defect steering circuit Memory defect steering circuit

1998-08-13

2001-02-20

Iqbal, Nadeem (Department: 2785)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S025000

Reexamination Certificate

active

06192486

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to computer chips with embedded memories and specifically to addressing defects in computer chips with embedded memories.
BACKGROUND OF THE INVENTION
It is a common occurrence for defects to occur in parts of computer memory chips with embedded memories which result in non-functional parts of the memories. Conventionally, redundancy schemes are used to “repair” such defects on stand-alone memories while embedded memories without redundancy schemes are discarded.
Chips with embedded memories contain numerous cells, each cell having the capability of storing a high or a low voltage representing a “1” bit or a “0” bit respectively. The cells are interconnected in a grid with each row of cells commonly referred to as a word line, a set of word lines being a memory array. Each array has a unique multiplexed address which is controlled by an address generator. This structure of a chip with embedded memory is well known in the art and will not be further discussed here.
When a defective memory array is found during manufacturing tests, the conventional redundancy scheme attempts to replace sections of the damaged array with a redundant bit or word line using fuses. The fuses connecting the defective array portion to the functioning portions of the chip are broken while the fuses which would connect the redundant bit or word line are activated. In this way, defective parts of the chip are replaced and repaired.
A problem with the conventional redundancy scheme is that fuses require additional area on the chip. This can be a heavy penalty for conventional chips which are already very dense. In addition, fuses require additional manufacturing processes which increases the process complexity and manufacturing cost.
Another problem is its limited utility to defects found during manufacturing tests. If defects are introduced into memory during use, they cannot be addressed. The computer may suffer a shut-down without advance warning which would cost a user valuable time. This is a particular problem for computers running critical applications.
Therefore, there exists a need for a circuit for addressing memory defects which minimizes additional area on the chip and has utility subsequent to manufacturing testing. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for bypassing defective sections of a memory array of a computer chip. A circuit in accordance with the present invention includes a register for controlling the effective size of the memory array based upon the detection of at least one defective section in the memory array, and a multiplexer for receiving an index address for the memory array and for the mapping of the index address based upon the register means. The circuit in accordance with the present invention does not use fuses to conduct repairs and thus does not require additional area on the chip for such fuses. As such, it eliminates the complications in the manufacturing process related to redundant cells. The circuit in accordance with the present invention dynamically manipulates the address of the array to bypass the defective regions of the array. Although the present invention results in a reduction in the overall size of the array, and thus may result in performance degradation, it allows for the continued operation of the chip. For an embedded memory, the chip need not be discarded. Importantly, unlike the conventional method, the circuit in accordance with the present invention has the ability to handle defects which are introduced during usage, and defect detection and bypass are initiated each time the computer is initialized. Thus, the present invention has utility subsequent to manufacturing testing. A chip with embedded memory which has the steering circuit of the present invention is thus more reliable than memory chips repaired with conventional methods.


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Goldman et al., Halt and start control for microprocessor systems, Derwent No. DD 153445A, 1—1, Jan. 1982.
IBM Technical disclosure Bulletin, Software control of memory scrubbing, TDB, NN911157, 1-2, Dec. 1991.

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