Memory correction system and method

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S201000

Reexamination Certificate

active

11214697

ABSTRACT:
An error correction system and method operable to identify and correct a memory module disposed within a computer memory system. In one embodiment, the memory system comprises a plurality of memory modules organized as a number of error correction code (ECC) domains, wherein each ECC domain includes a set of memory modules, each memory module comprising a plurality of memory devices. A module error correction engine is operable in association with a memory controller operably coupled to the plurality of memory modules, the module error correction engine operating to identify which one of the memory modules of a particular ECC domain is defective and thereby recover the defective memory module's data based on a redundant memory module associated with the particular ECC domain.

REFERENCES:
patent: 5619642 (1997-04-01), Nielson
patent: 5751939 (1998-05-01), Stiffler
patent: 6493843 (2002-12-01), Raynham
patent: 6715116 (2004-03-01), Lester et al.
patent: 6785835 (2004-08-01), MacLaren et al.
patent: 6845472 (2005-01-01), Walker et al.
patent: 6883131 (2005-04-01), Acton
patent: 6918007 (2005-07-01), Chang et al.
patent: 7187602 (2007-03-01), Wohlfahrt et al.
patent: 2004/0225943 (2004-11-01), Brueggen
patent: 2004/0225944 (2004-11-01), Brueggen
patent: 2005/0027891 (2005-02-01), Emmot et al.
patent: 2005/0071554 (2005-03-01), Thayer et al.
patent: 2005/0080958 (2005-04-01), Handgen et al.
patent: 2005/0160329 (2005-07-01), Briggs et al.
“IBM Chipkill Memory—Advanced ECC Memory for the IBM Netfinity 7000 M10”; IBM; pp. 1-6.
“White Paper: Understanding RAID”; http://www.ossi.net/raid/php; pp. 1-5.
Locklear, David; “Chipkill Correct Memory Architecture”; Dell; Technology Brief; Aug. 2000; pp. 1-4.
“RAID Technology White Paper”; Acer; Jul. 2001; pp. 1-19.
Dipert, Brian “Banish bad memories”; www.ednmag.com; Nov. 22, 2001; pp. 61-72.
Persson, Jimmy et al.; “RAID Systems”; Blekinge Institute of Technology, Sweden, Research Paper; Oct. 12, 2002; pp. 1-10.
Hewlett-Packard Dev. Co., Single-system reliability, availability, and serviceability on HP Integrity Superdome with emphasis on HP-UX, Jun. 2003 obtained from http: www.hp.com.
Malhotra, Manish and Trivedi, Kishor, Data integrity analysis of disk array systems with analytic modeling of coverage, Performance Evaluation,. vol. 22, 1995.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Memory correction system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory correction system and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory correction system and method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3853190

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.