Memory controlling method

Details Memory controlling method Memory controlling method

2006-09-08

2008-12-09

Elmore, Stephen C (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S105000, C711S213000, C711S220000

Reexamination Certificate

active

07464230

ABSTRACT:
A method for memory controlling is disclosed. It includes an embedded address generator and a controlling scheme of burst terminates burst, which could erase the latency caused by bus interface during the access of non-continuous addresses. Moreover, it includes a controlling scheme of anticipative row activating, which could reduce the latency across different rows of memory by data access. The method could improve the access efficiency and power consumption of memory.

REFERENCES:
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patent: 5193179 (1993-03-01), Laprade et al.
patent: 5426751 (1995-06-01), Sawamoto
patent: 5570202 (1996-10-01), Shishido et al.
patent: 5777629 (1998-07-01), Baldwin
patent: 5798770 (1998-08-01), Baldwin

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