Memory controllers with interleaved mirrored memory modes

Details Memory controllers with interleaved mirrored memory modes Memory controllers with interleaved mirrored memory modes

2006-03-21

2006-03-21

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S005000, C714S006130

Reexamination Certificate

active

07017017

ABSTRACT:
In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second primary data sections to the first and second memory channel interfaces, respectively, and send first and second redundant data sections to the second and first memory channel interfaces, respectively. The first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.

REFERENCES:
patent: 4518947 (1985-05-01), Poston et al.
patent: 4870643 (1989-09-01), Bultman et al.
patent: 5088081 (1992-02-01), Farr
patent: 5191584 (1993-03-01), Anderson
patent: 5367669 (1994-11-01), Holland et al.
patent: 5579277 (1996-11-01), Kelly
patent: 5604662 (1997-02-01), Anderson et al.
patent: 6130853 (2000-10-01), Wang et al.
patent: 6178135 (2001-01-01), Kang
patent: 6219287 (2001-04-01), Sugiyama
patent: 6393534 (2002-05-01), Chen et al.
patent: 6430702 (2002-08-01), Santeler et al.
patent: 6473339 (2002-10-01), De Ambroggi et al.
patent: 6785835 (2004-08-01), MacLaren et al.
patent: 6877076 (2005-04-01), Cho et al.
patent: 2003/0070055 (2003-04-01), Johnson et al.
patent: 2004/0093472 (2004-05-01), Dahlen et al.
patent: 0 755 009 (1997-01-01), None
patent: WO 02/086653 (2002-10-01), None
Digital Semiconductor 21172, Core Logic Chipset, Technical Reference Manual, .COPYRGT. Digital Equipment Corporation, Apr. 1996, Ch. 3 pp. 17-27; Ch. 4 pp. 49-61.
Rambus Inc., Direct RDRAM 128/144-MBIT (256K .times. 16/18.times.32s), Document DL0059, Version 1.1, pp. 1-66.
Zacharenia Xanthaki “A Memory Controller For Interleaving Over A Single Rambus” www.ics.forth.gr/proj/arch-vlsi/sw_arch/interlRambus.ps.gz, Feb., 1994.*.
“Preliminary Information, Direct Rambus Memory Controller (RMC2)”, www.rambus, pp. 1-18, Jul. 2000.*.
Copy of PCT Search Report date Nov. 5, 2004 (P15129PCT).
Copy of PCT Search Report date Nov. 5, 2004 (14529PCT).
Pending US Patent Appln. 10/290,889 entitled “Interleaved Mirrored Memory Systems” filed Nov. 11, 2002.

Affiliated with

Also associated with

Rating

Memory controllers with interleaved mirrored memory modes does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory controllers with interleaved mirrored memory modes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controllers with interleaved mirrored memory modes will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3575878