Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2001-04-07
2003-09-23
Kim, Hong (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S167000, C711S170000, C711S105000, C365S193000, C365S189080, C713S500000
Reexamination Certificate
active
06625702
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to the field of memory controllers.
BACKGROUND OF THE INVENTION
The purpose of a memory controller is to field and execute memory access requests (i.e., requests to read data from, and write data to, a number of memory modules). A memory access request may be initiated by either a central processing unit (CPU) or an input/output device (I/O device).
In the past, most memory controllers have been designed to access memory modules which are read and written via common clock data transmissions. That is, data bits are transmitted between a memory controller and a number of memory modules in sync with the rising edges of the memory controller's internal clock. However, there is a current push to design memory controllers which are capable of accessing double data rate (DDR) memory modules.
A DDR memory module is one which is read and written via source synchronous data transmissions. That is, data bits are transmitted between a memory controller and a number of memory modules in sync with the rising and falling edges of a strobe, with the strobe being generated by the component which sources the data. The strobe is then used by the component which receives the data for the purpose of capturing the data. Thus, a strobe is transmitted by the memory controller during a write operation, and a strobe is transmitted by a memory module during a read operation.
SUMMARY OF THE INVENTION
As is known by those skilled in the art, memory manufacturers produce, and computer systems use, a plurality of different memory module types. Unfortunately for the computer user, a given computer system is typically limited to using one memory module type (i.e., homogeneous memory modules). Thus, when a computer user wants to add to their computer's available memory, the computer user must determine precisely what type of memory their computer requires, and then locate and purchase that type of memory. Sometimes, a computer user decides not to upgrade their memory because, for example, the type of memory which their computer requires is too expensive, or the type of memory which their computer requires does not provide the kind of features they are seeking (e.g., the memory has low bandwidth, low speed, low capacity, etc.). Even within the category of DDR DIMMs (dual inline memory modules), there are numerous types of memory modules—only one of which is likely to be usable in a given computer system.
In accordance with the invention, disclosed herein are methods and apparatus for providing a memory controller with an ability to read and write memory modules comprised of non-homogenous data width RAM (random access memory) devices. Thus, a computer system which uses the new memory controller will provide its user with a number of options for memory upgrades—some of which may be more cost-effective, some of which may provide better performance, et cetera. The methods and apparatus are particularly relevant in the context of DDR memory modules, which may comprise DDR SDRAMs of 4, 8 and 16 bit data widths, as defined in JEDEC Standard No. 79 (published June 2000; hereinafter referred to as the “JEDEC DDR SDRAM Specification”).
One embodiment of the invention is embodied in a memory controller comprising a memory map storing indications of data/strobe ratios which are required to read and write memory modules coupled to the memory controller. The memory map is addressed during read and write cycles of the memory controller. The memory controller further comprises subsets of strobe driver circuits, wherein each of the subsets receives addressed indications of data/strobe ratios during the memory controller's write cycles. At least one of the subsets of strobe driver circuits generates strobes in response to only a portion of the addressed indications of data/strobe ratios (e.g., certain values of the addressed indications). The memory controller also comprises pluralities of strobe receiver circuits and data receiver circuits, as well as a number of multiplexers which associate at least some of the strobe receiver circuits with at least some of the data receiver circuits. Each of the multiplexers receives addressed indications of data/strobe ratios during the memory controller's read cycles, and in response to different indications, associates different ones of the strobe receiver circuits with the data receiver circuits.
The important advantages and objectives of the above and other embodiments of the invention will be further explained in, or will become apparent from, the accompanying description, drawings and claims.
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Hargis Jeffrey G.
Letey George T
Rentschler Eric M.
Hewlett--Packard Development Company, L.P.
Kim Hong
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