Memory controller with ring bus for interconnecting memory...

Details Memory controller with ring bus for interconnecting memory... Memory controller with ring bus for interconnecting memory...

2006-07-11

2010-12-07

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S151000

Reexamination Certificate

active

07849256

ABSTRACT:
Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.

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Form PCT/ISA/220, “PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” 2 pgs.
Form PCT/ISA/210, “PCT International Search Report,” 4 pgs.
Form PCT/ISA/237, “PCT Written Opinion of the International Searching Authority,” 5 pgs.

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